Vijay Savani

Employment

• Institute of Technology, Nirma Univerity Asst. Professor
  2005 - Present

Education

• Nirma Univestity Ph.D. in Engineering and Technology
  2011 - 2018
• Institute of Technology, Nirma University M. Tech in VLSI Design
  2009 - 2011
• Shantilal Shah Engineering College B.E.
  1996 - 2000

Projects & Funding

Projects & funding information is unavailable.

Publications (47)

• A hybrid 16-bit Ripple Carry Adder with Doublet Transmission Gate-based Compressor for performance boost
  Integration 2026 1 citation DOI: 10.1016/j.vlsi.2025.102594
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• Automatic vehicle accident detection and alerting notification using internet of things
  International Journal of Informatics and Communication Technology (IJ-ICT) 2025 0 citations DOI: 10.11591/ijict.v14i1.pp315-324
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• Efficient 1-Bit Hybrid Full Adder Design with Low Power Delay Product Using FinFET-TGDI Technology: Simulation and Comparative Study
  2025 1 citation DOI: 10.1007/978-981-97-5269-0_21
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• Design and Analysis of Low-Voltage and Low-Power 19T FinFET-TGDI-Based Hybrid Full Adders
  Journal of Circuits, Systems and Computers 2024 1 citation DOI: 10.1142/S0218126624500154
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• Emotion Recognition in Speech Using Convolutional Neural Networks (CNNs)
  Algorithms for Intelligent Systems 2024 0 citations DOI: 10.1007/978-981-97-0180-3_16
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• DESIGN AND SIMULATION OF CLOCK AND DATA RECOVERY CIRCUIT (CDR) IN 180NM CMOS TECHNOLOGY
  IJRAR - International Journal of Research and Analytical Reviews (IJRAR) 2021
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• Design and Simulation of Clock and Data Recovery Circuit (CDR) in 180nm CMOS Technology
  52nd Mid Term Symposium (MTS) on the theme Emerging Trends in ICT and Electronics 2021
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• Retinopathy based Diabetes Recognition using Convolution Neural Network
  INTERNATIONAL JOURNAL OF SCIENTIFIC & ENGINEERING RESEARCH 2021
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• Design and Implementation of Double Precision Floating Point Multiplier (FPM) on Reconfigurable Hardware Platform
  National Conference on Advancement in Communication, Electronics, Computer, and Automation Technology (ACECAT-2021) 2021
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• Performance analysis of Vedic mathematics algorithms on re-configurable hardware platform
  Sādhanā 2021 14 citations DOI: 10.1007/s12046-021-01605-4
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