DS
0000-0002-1136-1421 Employment
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Jaypee University of Engineering and Technology
Education
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JUET Ph.D2010 - 2017
Projects & Funding
Projects & funding information is unavailable.
Publications (12)
- An efficient reconfigurable floating point multiplier design for signal processing applications Save
- A Phase Modulation-Based Approach for Theft-Proof Electricity Distribution in India Using CDMA Technology Save
- An area-delay efficient single-precision floating-point multiplier for VLSI systems Save
- Area-delay efficient Radix-4 8×8 Booth multiplier for DSP applications Save
- Area-delay and energy efficient multi-operand binary tree adder Save
- Efficient diminished-1 modulo (2n + 1) adder using parallel prefix adder Save
- A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic Save
- Area-Delay and Energy-Efficient Throughput-Scalable VLSI Architecture for SDR Channelizer Save
- Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic Save
- Efficient architectures for VLSI implementation of 2-D discrete Hadamard transform Save