Basant Kumar Mohanty

Employment

• Sambalpur University Institute of Information Technology Director
  2021 - Present
• Mukesh Patel School of Technology Management and Engineering - Shirpur Campus Professor
  2018 - Present
• Jaypee University of Engineering and Technology Professor
  2003 - 2018
• Mody University of Science and Technology Assistant Professor
  2002 - 2003
• Birla Institute of Technology and Sciences, Pilani Lecturer
  2001 - 2002

Education

• Bhanja Vihar PhD
  1994 - 2000

Projects & Funding

Projects & funding information is unavailable.

Publications (50)

• Hardware Design for VLSI Implementation of FxLMS- and FsLMS-Based Active Noise Controllers
  Circuits, Systems, and Signal Processing 2017 DOI: 10.1007/s00034-016-0311-x
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• Efficient Design for Radix-8 Booth Multiplier and Its Application in Lifting 2-D DWT
  Circuits, Systems, and Signal Processing 2017 DOI: 10.1007/s00034-016-0349-9
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• A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic
  Integration, the VLSI Journal 2016 DOI: 10.1016/j.vlsi.2016.01.006
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• Area-Delay and Energy-Efficient Throughput-Scalable VLSI Architecture for SDR Channelizer
  Circuits, Systems, and Signal Processing 2016 DOI: 10.1007/s00034-015-0183-5
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• Efficient Parallel Architecture for Fixed-Coefficient and Variable-Coefficient FIR Filters Using Distributed Arithmetic
  Journal of Circuits, Systems and Computers 2016 DOI: 10.1142/S0218126616500730
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• LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2016 DOI: 10.1109/TVLSI.2015.2472964
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• A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2016 DOI: 10.1109/TVLSI.2015.2412556
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• Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT Using 9/7 and 5/3 Filters
  Proceedings of the IEEE International Conference on VLSI Design 2015 DOI: 10.1109/VLSID.2015.61
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• Novel block-formulation and area-delay-efficient reconfigurable interpolation filter architecture for multi-standard SDR applications
  IEEE Transactions on Circuits and Systems I: Regular Papers 2015 DOI: 10.1109/TCSI.2014.2349579
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• Memory-access aware work-load distribution for peak-temperature reduction of 3D multi-core embedded systems
  International Conference on Digital Signal Processing, DSP 2015 DOI: 10.1109/ICDSP.2015.7252085
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