Satish Maheshwaram

Employment

• National Institute of Technology Warangal Assistant Professor
  2018 - Present
• Marri Laxman Reddy Institute of Technology and Management Assistant Professor / Dean R&D of Institute
  2015 - 2018
• Cognizant Technology Solutions India Programmer Analyst Trainee
  2007 - 2008

Education

• Indian Institute of Technology Roorkee Ph.D. (Microelectronics and VLSI)
  2010 - 2015
• Indian Institute of Technology Roorkee M.Tech (Semiconductor Devices and VLSI Technology)
  2008 - 2010
• MVSR Engineering College B.E.
  2003 - 2007

Projects & Funding

Projects & funding information is unavailable.

Publications (23)

• Impact of Time Zero Variability and BTI Reliability on SiNW FET-Based Circuits
  IEEE Transactions on Device and Materials Reliability 2019 DOI: 10.1109/TDMR.2019.2949761
  +Save
• A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation
  2016 20th International Symposium on VLSI Design and Test, VDAT 2016 2017 DOI: 10.1109/ISVDAT.2016.8064852
  +Save
• Compact NBTI reliability modeling in Si nanowire MOSFETs and effect in circuits
  IEEE Transactions on Device and Materials Reliability 2017 DOI: 10.1109/TDMR.2017.2694709
  +Save
• Lateral silicon nanowire based standard cell design for higher performance
  2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 2017 DOI: 10.1109/APCCAS.2016.7803915
  +Save
• Performance and Variability Analysis of SiNW 6T-SRAM Cell Using Compact Model with Parasitics
  IEEE Transactions on Nanotechnology 2017 DOI: 10.1109/TNANO.2017.2735900
  +Save
• Vertical nanowire FET based standard cell design employing Verilog-A compact model for higher performance
  Communications in Computer and Information Science 2017 DOI: 10.1007/978-981-10-7470-7_24
  +Save
• Compact model for vertical silicon nanowire based device simulation and circuit design
  ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE) 2016 DOI: 10.1109/ISOCC.2015.7401675
  +Save
• Reduction of GIDL Using Dual Work-Function Metal Gate in DRAM
  2016 IEEE 8th International Memory Workshop, IMW 2016 2016 DOI: 10.1109/IMW.2016.7495287
  +Save
• Low power SRAM design for 14 nm GAA Si-nanowire technology
  Microelectronics Journal 2015 DOI: 10.1016/j.mejo.2015.10.016
  +Save
• Novel design methodology using L<inf>EXT</inf> sizing in nanowire CMOS logic
  IEEE Transactions on Nanotechnology 2014 DOI: 10.1109/TNANO.2014.2312078
  +Save