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Publications (10)
- Real Time Indoor Mapping Using Hexacopter Save
- Optimized Microcode BIST Architecture for Multiple Memory Cores in SoCs Save
- Optimized BIST architecture for memory cores and logic circuits using CLFSR Save
- Development of TI console framework for test automation of radio network controller Save
- Complete data and address generation for memory testing using modified LFSR structures Save
- BIST Architecture for Multiple RAMs in SoC Save
- Design and Implementation of Double Precision Floating Point Comparator Save
- Implementation of fast multiplier using modified Radix-4 booth algorithm with redundant binary adder for low energy applications Save
- VLSI design and comparative analysis of memory BIST controllers Save
- Implementation of extended open core protocol interface memory system using Verilog HDL Save