0000-0002-1836-1547 Employment
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Publications (12)
- Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation Save
- A Novel NOR Gate-Based Dynamic Power Gating Technique in SRAM Save
- Low power transistor level synthesis of finite state machines using a novel dual gating technique Save
- Low-power FSM synthesis based on automated power and clock gating technique Save
- An autonomous power and clock gating technique in SRAM-based FPGA Save
- Leakage Reduction of SRAM-Based Look-Up Table Using Dynamic Power Gating Save
- An Autonomous Clock Gating Technique in Finite State Machines Based on Registers Partitioning Save
- Design of new high-speed and low-energy dynamic PLA Save
- Layout-oriented look up table-based dual threshold approach to reduce leakage Save
- CG-in-PG architecture implementation for power reduction in FSMs Save