Sanjay Vidhyadharan

About

Dr. Sanjay Vidhyadharan is an Assistant Professor in the Electrical and Electronics Engineering group of Work Integrated Learning Programmes Division, BITS-Pilani. He graduated from Regional Engineering College (NIT), Bhopal, in 1994 and was commissioned in the Engineering branch of the Indian Air Force in Nov 1994. He served in the Indian Airforce for 22 years, working as Senior Engineering Officer, Chief Engineering Officer and Joint Director at various helicopter bases/Air HQs. He took pre-mature retirement from the IAF as Wing Commander in 2016 to pursue his passion for academics. He has immense experience in the maintenance of various kinds of helicopters.

He obtained his M.Tech. in Micro Electronics and VLSI Design from the Indian Institute of Technology Kharagpur in 2010. He completed his Ph.D. research work from BITS Pilani Hyderabad campus in Jan 2017-Jan 2020 and was awarded doctorate in Jun 2020.

Dr. Sanjay was a qualified instructor of IAF and had worked as Commanding Officer of a Premier Technical Training Institute of IAF. He has also worked as a Visiting Assistant Professor at BITS Pilani, Hyderabad Campus, from Feb 2020 to Aug 2021. His area of interest is Analog and Digital VLSI. He has published more than 20 publications in various international journals and conferences in low-power VLSI design.

Employment

• Birla Institute of Technology and Science - Hyderabad Campus Visting Faculty
  2020 - 2021
• Indian Air Force Wing Commander
  1994 - 2016

Education

• Birla Institute of Technology and Science - Hyderabad Campus Ph.D
  2017 - 2020
• Indian Institute of Technology Kharagpur M. Tech
  2008 - 2010
• Maulana Azad National Institute of Technology B.E
  1990 - 1994

Projects & Funding

Projects & funding information is unavailable.

Publications (13)

• TiO2−x–TiO2 Memristor Applications for Programmable Analog VLSI Circuits at 45 nm CMOS Technology Node
  Transactions on Electrical and Electronic Materials 2021 DOI: 10.1007/s42341-020-00253-5
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• An ultra-low-power CNFET based dual V ternary dynamic Half Adder
  Microelectronics Journal 2021 DOI: 10.1016/j.mejo.2020.104961
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• A novel ultra-low-power gate overlap tunnel FET (GOTFET) dynamic adder
  International Journal of Electronics 2020 DOI: 10.1080/00207217.2020.1740800
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• An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger
  Microelectronics Journal 2020
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• Suppression of Ambipolar Behavior and Simultaneous Improvement in RF Performance of Gate-Overlap Tunnel Field Effect Transistor (GOTFET) Devices
  Silicon 2020 DOI: 10.1007/s12633-020-00506-1
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• Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC
  Integration 2020 DOI: 10.1016/j.vlsi.2020.03.006
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• Innovative multi-threshold gate-overlap tunnel FET (GOTFET) devices for superior ultra-low power digital, ternary and analog circuits at 45-nm technology node
  Journal of Computational Electronics 2020 DOI: 10.1007/s10825-019-01440-1
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• An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications
  Analog Integrated Circuits and Signal Processing 2020 DOI: 10.1007/s10470-019-01561-4
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• A nanoscale gate overlap tunnel FET (GOTFET) based improved double tail dynamic comparator for ultra-low-power VLSI applications
  Analog Integrated Circuits and Signal Processing 2019 DOI: 10.1007/s10470-019-01487-x
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• An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET Devices
  2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) 2019 DOI: 10.1109/VLSID.2019.00087
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