R Sakthivel
Also known as: Sakthi
Vellore Institute of Technology, VIT University
0000-0002-1879-2080
About
Dr.Sakthivel R received Bachelor degree in Electrical Engineering from Madras University in 2000 and his M.E degree in Applied Electronics from Anna University in 2004. He has received his Doctorate in the area of Low Power High speed architecture development for signal processing and cryptography. He is currently working as an Associate Professor in the School of Electronics Engineering at Vellore Institute of Technology University, Vellore. His research area includes Low power VLSI Design, Developing High speed architecture for cryptography, Analog VLSI. He is a member ISTE, SSI and VLSI Society of India (VSI). He is the Co-author of Basic Electrical Engineering" Published by Sonaversity in the year 2001 and author of VLSI Design published by S.Chand in the year 2007. He has also published several technical papers in national and international conferences/ Journals. He has delivered around 50 Guest lectures / Invited talk and hands on workshop in the area of FPGA based System Design, Analog IC Design, Fulll Custom IC Design, RTL to GDSII, ASIC Design etc.
Employment
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Vellore Institute of Technology Associate dean , Professor
Education
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VIT University Doctor of Philosophy2009 - 2014
Projects & Funding
Projects & funding information is unavailable.
Publications (25)
- A review on selective in-memory computing processors: Potential alternative to AI-driven applications Save
- Multi-Parameter Comparative Study of Selective In-Memory Computing Processor Architectures for Performance Optimization in Accelerated Edge Computing Save
- Low-power artificial neuron networks with enhanced synaptic functionality using dual transistor and dual memristor Save
- Generalized Bio-Plausible Neuron Model with Refractoriness, Frequency Adaptation and Dynamic Threshold Save
- An energy-efficient hybrid CMOS spiking neuron circuit design with a memristive based novel T-type artificial synapse Save
- Enhancement of Convolutional Neural Network Hardware Accelerators Efficiency Using Sparsity Optimization Framework Save
- The Artificial Neuron: Built From Nanosheet Transistors to Achieve Ultra Low Power Consumption Save
- Neuron Network with a Synapse of CMOS transistor and Anti-Parallel Memristors for Low power Implementations Save
- Design of Artificial Neuron Network with Synapse Utilizing Hybrid CMOS Transistors with Memristor for Low Power Applications Save
- An efficient hardware implementation of the elliptic curve cryptographic processor over prime field, Save