Pritam Bhattacharjee

About

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https://sites.google.com/site/pritambhattacharjeevlsi/

Employment

• Vellore Institute of Technology - Chennai Campus Assistant Professor (Senior Grade 2)
  2023 - Present
• Amrita Vishwa Vidyapeetham Amrita School of Engineering Amritapuri Assistant Professor (Sr. Gd.)
  2020 - 2023
• Intel (India) Graduate Intern Technical
  2019 - 2020
• Bidyanidhi Institute of Technology & Management Lecturer
  2014 - 2015

Education

• National Institute of Technology, Arunachal Pradesh Ph.D Scholar
  2016 - 2020
• Heritage Institute of Technology M.Tech
  2011 - 2013
• Institute of Science & Technology B.Tech
  2007 - 2011

Projects & Funding

Projects & funding information is unavailable.

Publications (15)

• On-chip supply noise in multiprocessors: impact and clock gating inspired mitigation strategies
  International Journal of Electronics 2024 DOI: 10.1080/00207217.2022.2158493
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• Performance of Automated Machine Learning Based Neural Network Estimators for the Classification of PCOS
  2023 DOI: 10.1007/978-981-99-3478-2_7
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• Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2022 DOI: 10.1109/TCAD.2021.3099438
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• Study of Machine Learning Techniques to Mitigate Fraudulent Transaction in Credit Cards
  2022 DOI: 10.1007/978-981-19-0840-8_42
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• A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time
  Circuits, Systems, and Signal Processing 2021 DOI: 10.1007/s00034-020-01546-z
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• Understanding of On-Chip Power Supply Noise: Suppression Methodologies and Challenges
  Recent Trends in Communication Networks [Working Title] 2019 DOI: 10.5772/intechopen.90378
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• A variation tolerant data dependent clock gating approach for PSN attenuated low power digital IC
  Ain Shams Engineering Journal 2019 DOI: 10.1016/j.asej.2018.11.010
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• Variation aware intuitive clock gating to mitigate on-chip power supply noise
  International Journal of Electronics 2018 DOI: 10.1080/00207217.2018.1460873
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• A 90 nm leakage control transistor based clock gating for low power flip flop applications
  Midwest Symposium on Circuits and Systems 2017 DOI: 10.1109/MWSCAS.2016.7870034
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• Estimation of power dissipation in ternary quantum dot cellular automata cell
  Journal of Low Power Electronics 2017 DOI: 10.1166/jolpe.2017.1485
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