0000-0002-2007-7828 Employment
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VNRVJIET Teaching2013 - Present
Education
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JNTU PhD2009 - 2018
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VNR VJIIET M.TECH2005 - 2007
Projects & Funding
Projects & funding information is unavailable.
Publications (40)
- Design and Analysis of Ultra-Low Power and High-Speed Configurable Logic Block Using a Memory Element for FPGA Save
- Design and Analysis of Low Power and High-Speed FIR Filter Using Advanced Optimization Techniques Save
- Implementation of Radix-4 Booth Multiplier using Data Static Segmentation Save
- Implementation Of An Ultra-Low-Power High-Speed CLB Using A Memory Element And Its Power Dissipation Analysis For FPGA with Quantum-dot Cellular Automata Save
- Design the Power Evaluation of a Highly Efficient Low-Complex Adder Implementation Using Inequality Gate by Quantum-Dot Cellular Automata Save
- GAAFET-based Hybrid Sense Amplifier for High Speed Applications Save
- Low Power and High Throughput 12-Tap FIR Filter Using Unfolding Algorithm Save
- Extraction of Satellite Data and Generation of C/A Codes for GPS Signals on FPGA Save
- Development of an Efficient Algorithm for Acquisition of GNSS Receiver Signals using Parallel Code Phase Search Technique Save
- Design of Strong-Arm Latch Comparator for Low Power 12-bit SAR ADC Save