Bhaskar Manickam
Also known as: Bhaskar M
National Institute of Technology Tiruchirappalli
About
M. Bhaskar received the B.E. degree in Electronics and Communication Engineering from Bharathiar University, Coimbatore, India, in 1992, M.E. degree in Microwave and Optical Engineering from Madurai Kamaraj University, Madurai, India in 1995 and Ph.D. Degree in High speed on-chip Interconnect design from National Institute of Technology, Tiruchirappalli, India in 2015.
He worked as project trainee in Antenna Division, Indian Space Research Organization (ISRO), Bangalore, India from July 1994 to February 1995. He worked as faculty in Shanmuga College of Engineering (now Sastra University), Thanjavur, India from June 1995 to April 1997. Since 1997, he has been with the faculty of the National Institute of Technology, Trichy (Formerly known as Regional Engineering College, Trichy). Currently he is the Professor of the Electronics and Communication Department.
He has coauthored one book and has published numerous papers in Journals, international and national conferences out of which several of them have been selected for the best paper award. He has done many projects using Programmable DSPs. His research interests include Architecture and applications of DSPs, On-chip RF wireless transceivers, Low power system on a single chip (SOC) design, the design and performance analysis of high speed transceivers for on-chip interconnects and VLSI design for Biomedical applications.
Employment
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National Institute of Technology Tiruchirappalli Professor
Education
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National Institute of Technology Tiruchirappalli Bachelor of Engineering, Master of Engineering and Ph.D.
Projects & Funding
Projects & funding information is unavailable.
Publications (96)
- Improved low noise and highly linear 5–6 GHz LNA for Wi-Fi 6/6E-IEEE 802.11ax standard 5G application Save
- FPGA Implementation of High-Performance Adders and Their Performance Comparison with Virtual I/O Save
- A fully integrated 2.4 GHz inductorless high gain low NF cascade-LNA Co-designed to on-chip 3D antenna for IoT based implantable devices Save
- Power-Efficient Modified Multi-Gate High-Linear LNA for EHT Wireless Applications Save
- Design and Simulation of High Gain LNA Using 28nm Technology Save
- A 3.5GHz Reconfigurable 2-Stage Cascode CMOS LNA with HPF Noise Matching & Body Bias for 5G NR n78 Band Applications Save
- Dual-tuned high-swing variable-gain amplifier with enhanced dB-linear control Save
- FPGA Implementation of Modified Lightweight 128-Bit AES Algorithm for IoT Applications Save
- Design and FPGA Implementation of Pre-computation Based Radix-4 Hyperbolic CORDIC for Direct Digital Synthesis Save
- Cryogenic optical packaging of nanophotonic devices with coupling loss < 1 dB Save