Dhanaraj Jagalchandran Kakkanattu

Employment

• National Institute of Technology Assistant Professor
  2005 - Present

Education

• Indian Institute of Technology Delhi Ph.D.
  2010 - 2017
• National Institute of Technology M.Tech. (Digital Systems and Communication Engineering)
  2004 - 2006
• National Institute of Technology B.Tech. (ECE)
  1999 - 2003

Projects & Funding

Projects & funding information is unavailable.

Publications (16)

• MOSFET only low power sub‐bandgap voltage reference by subtraction of slope compensated proportional‐to‐absolute‐temperature voltage references
  International Journal of Circuit Theory and Applications 2024 DOI: 10.1002/cta.3831
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• Energy Efficient and Secure Neural Network–based Disease Detection Framework for Mobile Healthcare Network
  ACM Transactions on Privacy and Security 2023 DOI: 10.1145/3585536
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• Investigation of switching and inverter characteristics of Recessed-Source/Drain (Re–S/D) Silicon-on-Insulator (SOI) Feedback Field Effect Transistor (FBFET)
  Microelectronics Journal 2023 DOI: 10.1016/j.mejo.2023.105855
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• State Separate Modular Modeling Methodology of Multioutput DC–DC Converters
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2023 DOI: 10.1109/tcad.2022.3186492
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• Planar CMOS and multigate transistors based wide-band OTA buffer amplifiers for heavy resistance load
  Facta universitatis - series: Electronics and Energetics 2022 DOI: 10.2298/fuee2201013j
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• Private and Energy-Efficient Decision Tree-Based Disease Detection for Resource-Constrained Medical Users in Mobile Healthcare Network
  IEEE Access 2022 DOI: 10.1109/access.2022.3149771
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• A novel tunable gain CMOS buffer amplifier for large resistive loads
  Integration 2021 DOI: 10.1016/j.vlsi.2020.10.007
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• SPCOR: a secure and privacy‐preserving protocol for mobile‐healthcare emergency to reap computing opportunities at remote and nearby
  IET Information Security 2020 DOI: 10.1049/iet-ifs.2020.0086
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• MOSFETs-only sub-1-V voltage references for ultra-low-power applications
  Analog Integrated Circuits and Signal Processing 2020 DOI: 10.1007/s10470-020-01619-8
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• A low power architecture of real time stereo vision algorithm using discrete cosine transform
  IEEE Region 10 Annual International Conference, Proceedings/TENCON 2017 DOI: 10.1109/TENCON.2017.8227949
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