Chaithanya Mannepalli

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Publications (6)

• Design of a High Speed and Low Power Sample and Hold Circuit for 16 Bit ADC
  International Journal of Innovative Technology and Exploring Engineering 2019 DOI: 10.35940/ijitee.b1056.1292s319
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• 1.5mW,14.68V/µS-low power and high speed comparator design for ADC applications
  International Journal of Innovative Technology and Exploring Engineering 2019 DOI: 10.35940/ijitee.F1268.0486S419
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• A 2.2 V-voltage reference circuit design with TC of 35.49 ppm/o C for low power DAC applications
  International Journal of Innovative Technology and Exploring Engineering 2019 DOI: 10.35940/ijitee.F1269.0486S419
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• Design of a two stage operational amplifier with zero compensation for accurate bandgap reference circuit
  Acta Physica Polonica A 2019 DOI: 10.12693/APhysPolA.135.977
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• FinFET modelling using TCAD
  Lecture Notes in Electrical Engineering 2018 DOI: 10.1007/978-981-10-4280-5_21
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• Modified low-power hybrid 1-bit full adder
  Lecture Notes in Electrical Engineering 2018 DOI: 10.1007/978-981-10-4280-5_20
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