VJ
Vineet Jaiswal
UPES, DIT University, National Institute of Technology Kurukshetra, Teerthanker Mahaveer University
Employment
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UPES Assistant Professor Senior Scale2025 - Present
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DIT University Assistant Professor2025 - 2025
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Teerthanker Mahaveer University Assistant Professor2014 - 2021
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GBPUA&T Teaching Personnel2011 - 2012
Education
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National Institute of Technology Kurukshetra Ph.D2021 - 2025
Projects & Funding
Projects & funding information is unavailable.
Publications (9)
- Placement and routing approach for MQCA-based designs with BFS and A* algorithms Save
- Run-time reconfigurable nanomagnetic logic gates and comparator designs using very high-permeability material Save
- MQCA-based dipole coupled multiplexer design using permalloy Save
- A Novel Approach to Design Multiplexer Using Magnetic Quantum-Dot Cellular Automata Save
- High-Speed Comparator and Parity Generator Towards Simplified Clocking Circuit in QCA Technology Save
- Stick Diagram Representation for MQCA-based Multiplexer Save
- A Novel Approach to Design NML-based Programmable Input Rotating Majority Gate Save
- Novel approach for the design of efficient full adder in MQCA Save
- High Speed Comparator and Parity generator in QCA based on optimal XOR structure Save