Subhasis Bhattacharjee

Employment

• Indian Institute of Technology Jammu Associate Professor
  2019 - Present
• National Institute of Advanced Studies Technical Head
  2019 - 2019
• Adobe Systems India
  2017 - 2019
• Synopsys India Pvt. Ltd. Staff R & D Engineer
  2013 - 2017
• University of Bristol Post-Doc Research Assistant
  2012 - 2013
• Microsoft India R&D Pvt Ltd
  2011 - 2012
• Synopsys Inc
  2007 - 2011
• Wipro (India) Senior Software Engineer
  1998 - 2000

Education

• Indian Statistical Institute Ph. D.
  2007 - 2011
• Indian Statistical Institute M. Tech.
  1996 - 1998
• Sardar Vallabhbhai National Institute of Technology B. Eng.
  1992 - 1996

Projects & Funding

Projects & funding information is unavailable.

Publications (11)

• A new fast heuristic for labeling points
  2009 DOI: 10.1016/j.ipl.2009.01.011
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• Theory meets practice
  2009 DOI: 10.1145/1596543.1596546
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• Distributed data gathering scheduling in multihop wireless sensor networks for improved lifetime
  Proceedings - International Conference on Computing: Theory and Applications, ICCTA 2007 2007 DOI: 10.1109/ICCTA.2007.53
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• Distributed Node-Based Transmission Power Control for Wireless Ad Hoc Networks
  2006 DOI: 10.1007/11951957_5
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• Distributed algorithm for power aware connected dominating set for efficient routing in mobile ad hoc networks
  ISAHUC' 06 - Proceedings of 2006 International Symposium on Ad Hoc and Ubiquitous Computing 2006 DOI: 10.1109/ISAHUC.2006.4290650
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• Test pattern generation for power supply droop faults
  Proceedings of the IEEE International Conference on VLSI Design 2006 DOI: 10.1109/VLSID.2006.158
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• Distributed time slot assignment in wireless ad hoc networks for STDMA
  Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 2005 DOI: 10.1007/11604655_13
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• Fast FPGA placement using space-filling curve
  Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL 2005 DOI: 10.1109/FPL.2005.1515757
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• LPRAM: A low power DRAM with testability
  Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 2004
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• LPRAM: A novel methodology for low-power high-performance RAM design with testability
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2004 DOI: 10.1109/TCAD.2004.826581
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