HARSH SOHAL

About

Harsh Sohal received the B. Tech. degree in electronics and instrumentation engineering from Punjab Technical University, India, in 2005, and M. Tech. degree in very large scale integrated circuit design automation & techniques from the National Institute of Technology, Hamirpur, India in 2008. He received his Ph. D. degree, while working for bio-impedance based instrumentation system design, from the department of biomedical engineering, Kyung Hee University, South Korea in the year 2014.His research interests include ultra-low-power medical electronics devices, implantable medical electronics, FPGA design, biomedical instrumentation, biomedical signal processing and computing.
Dr. Sohal is life member of biomedical engineering society of India.

Employment

• Jaypee University of Information Technology Associate Professor
  2022 - Present
• Jaypee University of Information Technology Assistant professor
  2017 - 2022
• Chitkara University Assistant Director | Research
  2015 - 2017
• Dr BR Ambedkar National Institute of Technology Assistant Professor
  2014 - 2014
• National Institute of Technology Hamirpur Lecturer
  2008 - 2009
• Recorders and Medicare Systems Private Limited Engineer R & D
  2005 - 2006

Education

• Kyung Hee University - Global Campus Ph. D.
  2009 - 2014
• National Institute of Technology Hamirpur M. Tech.
  2006 - 2008
• Punjab Technical University B. Tech.
  2001 - 2005

Projects & Funding

Projects & funding information is unavailable.

Publications (26)

• A novel parallel prefix adder for optimized Radix-2 FFT processor
  Multidimensional Systems and Signal Processing 2021 DOI: 10.1007/s11045-021-00772-1
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• A Novel ASIC-Based Variable Latency Speculative Parallel Prefix Adder for Image Processing Application
  Circuits, Systems, and Signal Processing 2021 DOI: 10.1007/s00034-021-01741-6
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• COMPUTER-AIDED DIAGNOSTIC SYSTEM for FEATURE-BASED CLASSIFICATION USING HEART RATE VARIABILITY
  Biomedical Engineering - Applications, Basis and Communications 2020 DOI: 10.4015/S101623722050009X
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• Design and Analysis of High-Speed Parallel Prefix Adder for Digital Circuit Design Applications
  2020 International Conference on Computational Performance Evaluation, ComPE 2020 2020 DOI: 10.1109/ComPE49325.2020.9200064
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• Design and Implementation of Robust Low Power ECG Pre-processing Module
  IETE Journal of Research 2020 DOI: 10.1080/03772063.2020.1725660
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• FPGA-based parallel prefix speculative adder for fast computation application
  PDGC 2020 - 2020 6th International Conference on Parallel, Distributed and Grid Computing 2020 DOI: 10.1109/PDGC50313.2020.9315783
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• Multistage classification of arrhythmia and atrial fibrillation on long-term heart rate variability
  Journal of Engineering Science and Technology 2020
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• Optimized Crosstalk Circuit for Long Wire Copper Interconnects using 45nm CMOS Inverter
  Proceedings of 2020 IEEE International Women in Engineering (WIE) Conference on Electrical and Computer Engineering, WIECON-ECE 2020 2020 DOI: 10.1109/WIECON-ECE52138.2020.9397927
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• Statistical Analysis of HRV Parameters for the Detection of Arrhythmia
  International Journal of Image and Graphics 2020 DOI: 10.1142/S0219467820500369
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• FPGA implementation of power-efficient ECG pre-processing block
  International Journal of Recent Technology and Engineering 2019
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