Huirem Bharat Meitei

Employment

• NEHU Guest Lecturer
  2026 - Present
• Indian Institute of Information Technology Senapati, Manipur Project Manager
  2025 - Present
• Bechtel India Pvt Ltd Design engineer
  2017 - Present
• Cadsys India PVT Ltd Technical lead
  2015 - Present

Education

• Jawaharlal Nehru Technological University - Kakinada Mtech
  2015 - 2017
• Jawaharlal Nehru Technological University - Kakinada B.Tech
  2011 - 2015

Projects & Funding

Projects & funding information is unavailable.

Publications (7)

• FPGA design and implementation of TRNG architecture using ADPLL based on fir as loop filter
  Analog Integrated Circuits and Signal Processing 2025 DOI: 10.1007/s10470-024-02295-8
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• Design and Implementation of Multiple Ring Oscillator-Based TRNG Architecture by Using ADPLL
  IEEE Access 2025 DOI: 10.1109/ACCESS.2025.3527507
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• FPGA-Based True Random Number Generator Architecture Using 15-Bit LFSR and ADPLL
  Lecture Notes in Electrical Engineering 2024 DOI: 10.1007/978-981-99-4713-3_27
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• Implementation of a secure wireless communication system using true random number generator for internet of things
  Indonesian Journal of Electrical Engineering and Computer Science 2023 DOI: 10.11591/ijeecs.v30.i2.pp982-992
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• FPGA Implementation of a Wireless Communication System for Secure IR Sensor Data Transmission using TRNG
  International Journal of Engineering Trends and Technology 2022 DOI: 10.14445/22315381/ijett-v70i7p223
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• FPGA Implementation of True Random Number Generator Architecture Using All Digital Phase-Locked Loop
  IETE Journal of Research 2022 DOI: 10.1080/03772063.2021.1963333
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• FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter
  SN Applied Sciences 2022 DOI: 10.1007/s42452-022-04981-6
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