Dr. Indranil Hatai

Employment

• Mentor Graphics (United States) Member of Consulting Staff
  2024 - Present
• MathWorks (United States) Senior Application Engineer
  2022 - 2024
• SRM University AP Assistant Professor
  2021 - 2022

Education

• Indian Institute of Technology Kharagpur PhD
  2011 - 2017

Projects & Funding

Projects & funding information is unavailable.

Publications (16)

• Adopting artificial intelligence algorithms for remote fetal heart rate monitoring and classification using wearable fetal phonocardiography
  Applied Soft Computing 2024 DOI: 10.1016/j.asoc.2024.112049
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• A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical–Horizontal Common Sub-Expression Elimination Algorithm
  IEEE Transactions on Circuits and Systems I: Regular Papers 2018 DOI: 10.1109/TCSI.2017.2719053
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• An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis
  IEEE Transactions on Circuits and Systems I: Regular Papers 2015 DOI: 10.1109/TCSI.2015.2388838
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• An efficient VLSI architecture of a reconfigurable pulse-shaping fir interpolation
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2015 DOI: 10.1109/TVLSI.2014.2321171
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• FPGA implementation of a fetal heart rate measuring system
  Proceedings of 2013 2nd International Conference on Advances in Electrical Engineering, ICAEE 2013 2013 DOI: 10.1109/ICAEE.2013.6750325
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• Reconfigurable architecture of a RRC fir interpolator for multi-standard digital up converter
  Proceedings - IEEE 27th International Parallel and Distributed Processing Symposium Workshops and PhD Forum, IPDPSW 2013 2013 DOI: 10.1109/IPDPSW.2013.188
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• A high-speed low-power low-latency pipelined ROM-less DDFS
  Communications in Computer and Information Science 2011 DOI: 10.1007/978-3-642-17881-8_11
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• A new high-performance digital FM modulator and demodulator for software-defined radio and its FPGA implementation
  International Journal of Reconfigurable Computing 2011 DOI: 10.1155/2011/342532
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• ASIC implementation of a 512-point FFT/IFFT processor for 2D CT image reconstruction algorithm
  TechSym 2011 - Proceedings of the 2011 IEEE Students' Technology Symposium 2011 DOI: 10.1109/TECHSYM.2011.5783849
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• Programmable common baseband modulator for software defined radio system
  International Journal of Signal and Imaging Systems Engineering 2011 DOI: 10.1504/IJSISE.2011.043775
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