MANIVANNAN T S

Employment

Employment history is unavailable.

Education

• National Institute of Technology Tiruchirappalli Ph.D
  2018 - 2023
• Government College of Technology VLSI design
  2016 - 2018
• Alagappa Chettiar College of Engineering and Technology BE
  2010 - 2014

Projects & Funding

Projects & funding information is unavailable.

Publications (5)

• Ambipolar current suppression in drain elevated TFET using a novel extended drain structure with a moderate doping profile
  Microelectronics Journal 2024 DOI: 10.1016/j.mejo.2024.106302
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• Optimization of DE-QG TFET using novel CIP and DCT techniques
  Microelectronics Journal 2024 DOI: 10.1016/j.mejo.2024.106097
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• A Review of Engineering Techniques to Suppress Ambipolarity in Tunnel FET
  Silicon 2022 DOI: 10.1007/s12633-021-01018-2
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• A Novel Design Approach to Implement Multi-port Register Files Using Pulsed-Latches
  Communications in Computer and Information Science 2019 DOI: 10.1007/978-981-13-5950-7_44
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• A 4-READ 2-WRITE Multi-Port Register File Design Using Pulsed-Latches
  Proceedings of the 2nd International Conference on Electronics, Communication and Aerospace Technology, ICECA 2018 2018 DOI: 10.1109/ICECA.2018.8474898
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