Brinda Bhowmick

About

Currently, she is a Professor in Electronics and Communication Engineering Department of NIT Silchar since July 2022. She has 19 years teaching experience. She achieved Visvesvaraya Young Faculty Research Fellowship in January 2018 from MeitY Government of India. She has authored 108 SCI/ SCIE International Journal papers, 32 conference papers, 15 book chapters and published two patents and three patents are in granted status. She has authored one book in Cambridge Scholars publisher UK. Eight Ph.D. scholars are awarded Ph.D. degree under her guidance.

Her research interest is simulation and modelling of various semiconductor devices like TFET, SBMOS, HEMT, FINFET, Graphene FET, Tunnel diode including Group III-V materials, 2D materials, and their applications in analog and digital circuits and sensors.

Employment

• National Institute of Technology Silchar Professor
  2007 - 2021

Education

Education history is unavailable.

Projects & Funding

Projects & funding information is unavailable.

Publications (147)

• An Analytical Approach to Study the Impact of Traps on Ge-Source Double Gate PNPN TFET
  IETE Journal of Research 2023 DOI: 10.1080/03772063.2023.2217794
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• Analysis of the Impact of Interface Trap Charges on the Analog/RF Performance of a Graphene Nanoribbon Vertical Tunnel FET
  Journal of Electronic Materials 2023 DOI: 10.1007/s11664-023-10615-3
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• Compact drain current model of a double-gate raised buried oxide TFET for integrated circuit application
  Journal of Computational Electronics 2023 DOI: 10.1007/s10825-023-02077-x
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• Dielectric-Modulated Biosensor Based on Vertical Tunnel Field-Effect Transistor
  Smart Innovation, Systems and Technologies 2023 DOI: 10.1007/978-981-19-7107-5_9
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• Effect of Lateral Straggle Parameter on Hetero Junction Dual Gate Vertical Tfet
  SSRN 2023 DOI: 10.2139/ssrn.4425258
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• Effect of curie temperature on electrical parameters of NC-FinFET and digital switching application of NC-FinFET
  Microelectronics Journal 2023 DOI: 10.1016/j.mejo.2023.105892
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• Effect of lateral straggle parameter on Hetero Junction Dual Gate Vertical TFET
  Microelectronics Journal 2023 DOI: 10.1016/j.mejo.2023.105845
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• Effects of Ferro-thickness and Temperature on Electrical Performance of Si:HfO2based NC-FinFET
  2023 11th International Symposium on Electronic Systems Devices and Computing, ESDC 2023 2023 DOI: 10.1109/ESDC56251.2023.10149857
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• Impact of traps on DC, analog/RF, and linearity performance of Ferro-TFET
  Silicon 2023 DOI: 10.1007/s12633-022-02167-8
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• Investigation of a dual gate pocket-doped drain engineered tunnel FET and its reliability issues
  Applied Physics A: Materials Science and Processing 2023 DOI: 10.1007/s00339-023-06394-7
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