UM
Umayia Mushtaq
Indian Institute of Technology Jammu, Jamia Millia Islamia, Shri Mata Vaishno Devi University
0000-0002-3668-8009
Employment
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Indian Institute of Technology Jammu Postdoctoral Fellow2025 - Present
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Jamia Millia Islamia Assistant Professor (Contractual)2024 - 2025
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Jamia Millia Islamia Guest Faculty2024 - 2025
Education
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Shri Mata Vaishno Devi University MTECH2017 - 2019
Projects & Funding
Projects & funding information is unavailable.
Publications (14)
- Comparative Robustness Analysis of Different Adder Topologies Using ASAP7 FinFET Technology Save
- Design and Implementation of Multifunctional Logic Circuits Using SRAM Cells Utilizing In-Memory Computing Concept Save
- An energy and area-efficient spike frequency adaptable LIF neuron for spiking neural networks Save
- Impact of Variability on Novel Transistor Configurations in Adder Circuits at 7nm FinFET Technology Save
- INDIDO: A novel low-power approach for domino logic circuits Save
- A Novel D-Latch Design for Low-Power and Improved Immunity Save
- LCINDEP: a novel technique for leakage reduction in FinFET based circuits Save
- A Novel Energy Efficient and Process Immune Schmitt Trigger Circuit Design Using FinFET Technology Save
- Design and Analysis of Energy-Efficient Logic Gates Using INDEP Short Gate FinFETs at 10 nm Technology Node Save
- Energy Efficient and Variability Immune Adder Circuits using Short Gate FinFET INDEP Technique at 10nm technology node Save