Sajid Khan

Employment

• Cisco Systems India ASIC Verification Engineer
  2023 - Present
• Intel (India) SOC Design Engineer
  2019 - 2023
• Indian Institute of Technology Indore Researcher

Education

• Indian Institute of Technology Indore Doctorate

Projects & Funding

Projects & funding information is unavailable.

Publications (13)

• Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications
  Electronics 2021 DOI: 10.3390/electronics10141718
  +Save
• D flip-flop based TRNG with zero hardware cost for IoT security applications
  Microelectronics Reliability 2021 DOI: 10.1016/j.microrel.2021.114098
  +Save
• On-Chip Adaptive VDD Scaled Architecture of Reliable SRAM Cell With Improved Soft Error Tolerance
  IEEE Transactions on Device and Materials Reliability 2020 DOI: 10.1109/tdmr.2020.3019135
  +Save
• An energy‐efficient data‐dependent low‐power 10T SRAM cell design for LiFi enabled smart street lighting system application
  International Journal of Numerical Modelling: Electronic Networks, Devices and Fields 2020 DOI: 10.1002/jnm.2766
  +Save
• Utilizing manufacturing variations to design a tri-state flip-flop PUF for IoT security applications
  Analog Integrated Circuits and Signal Processing 2020 DOI: 10.1007/s10470-020-01642-9
  +Save
• A symmetric D flip-flop based PUF with improved uniqueness
  Microelectronics Reliability 2020 DOI: 10.1016/j.microrel.2020.113595
  +Save
• ASIC Implementation Of Biologically Inspired Spiking Neural Network
  2019 9th International Conference on Emerging Trends in Engineering and Technology - Signal and Information Processing (ICETET-SIP-19) 2019 DOI: 10.1109/icetet-sip-1946815.2019.9092079
  +Save
• An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications
  Microelectronics Journal 2019 DOI: 10.1016/j.mejo.2019.104605
  +Save
• A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations
  Communications in Computer and Information Science 2019 DOI: 10.1007/978-981-13-5950-7_18
  +Save
• An Ultra Low Power AES Architecture for IoT
  Communications in Computer and Information Science 2019 DOI: 10.1007/978-981-32-9767-8_29
  +Save