Satyam Shukla

About

Dr. Satyam Shukla is currently working as Technical Lead in R&D department of STMicroelectronics. Before joining his current position, he completed his doctorate from IIT Patna in VLSI architectural design. He graduated with an M. Tech. in 2016 and B. Tech in 2013.

With over four years of post-Ph.D. industrial experience as a Technical Lead in R&D at STMicroelectronics, successful tapeouts of multiple chips, and prior involvement in the SMDP-C2SD project under Visvesvaraya Ph.D. Scheme of MeitY, I aim to drive cutting-edge research, promoting industry-academia collaboration and enabling impactful advancements in indigenous semiconductor design and manufacturing.

His research interest includes Processor microarchitecture design, fault-tolerant VLSI architectural design, Digital VLSI design, FPGA-based system design, ASIC implementations, and system-on-chip design.

Employment

• STMicroelectronics (India) Technical Lead
  2023 - 2025
• Synopsys Inc. ASIC Digital Design Engineer Sr. -1
  2022 - 2023
• Semi-Conductor Laboratory Project Trainee
  2015 - 2016

Education

• Indian Institute of Technology Patna PhD
  2017 - 2022

Projects & Funding

Projects & funding information is unavailable.

Publications (8)

• Efficient piecewise approximate multipliers for fast and error-tolerant convolution operations
  Integration 2026 DOI: 10.1016/j.vlsi.2026.102849
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• A parallel ring streaming dataflow based convolution array architecture for CNN accelerator
  IEEE Embedded Systems Letters 2025 DOI: 10.1109/les.2025.3623654
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• An Efficient Fault-Tolerant Instruction Decoder for RISC-V Based Dual-Core Soft-Processors
  IEEE Transactions on Circuits and Systems I: Regular Papers 2023 DOI: 10.1109/TCSI.2023.3315604
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• An energy-efficient single-cycle RV32I microprocessor for edge computing applications
  Integration 2023 DOI: 10.1016/j.vlsi.2022.09.005
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• A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications
  IEEE Access 2022 DOI: 10.1109/ACCESS.2022.3169495
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• Design and ASIC Implementation of a Reconfigurable Fault-Tolerant ALU for Space Applications
  2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) 2019 DOI: 10.1109/ises47678.2019.00042
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• Modelling and mitigation of single-event upset in CMOS voltage-controlled oscillator
  Sādhanā 2018 DOI: 10.1007/s12046-018-0945-4
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• Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET
  Active and Passive Electronic Components DOI: https://doi.org/10.1155/2017/5947819
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