Suhas Shirol

Employment

• Mangalore Institute of Technology & Engineering Assistant Professor
  2026 - Present
• KLE Technological University
  2012 - 2025

Education

• KLE Technological University PhD
  2017 - 2025
• B V B College of Engg & Tech M.Tech
  2010 - 2012

Projects & Funding

Projects & funding information is unavailable.

Publications (24)

• Designing Power-Efficient BIST Architecture: Leveraging Reversible Logic for Scalable Digital Systems
  Journal of Electrical Systems 2024 DOI: 10.52783/jes.2053
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• Design and Implementation of ASIC for Time Recorder in TSMC 180 nm CMOS Technology
  Communications in Computer and Information Science 2021 DOI: 10.1007/978-981-16-5048-2_22
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• Design and Implementation of Mixed Signal ASIC-Event Logger in TSMC 0.18 µm CMOS Technology
  2021 DOI: 10.1007/978-981-33-4866-0_55
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• A novel design and implementation of 8-bit and 16-bit hybrid ALU
  Advances in Intelligent Systems and Computing 2020 DOI: 10.1007/978-3-030-16657-1_4
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• Towards sustainable integrated model for skill development: A collaborative approach
  Procedia Computer Science 2020 DOI: 10.1016/j.procs.2020.05.099
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• A novel design and implementation of 32-bit hybrid ALU
  Lecture Notes in Networks and Systems 2019 DOI: 10.1007/978-981-13-7150-9_25
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• Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology
  Communications in Computer and Information Science 2019 DOI: 10.1007/978-981-32-9767-8_11
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• Design and implementation of 8-bit LFSR, Bit-Swapping LFSR and weighted random test pattern generator: A performance improvement
  Proceedings of the International Conference on Intelligent Sustainable Systems, ICISS 2019 2019 DOI: 10.1109/ISS1.2019.8908063
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• Micro - Strip patch antenna using various types of feeding techniques: An implementation
  Proceedings of the International Conference on Intelligent Sustainable Systems, ICISS 2019 2019 DOI: 10.1109/ISS1.2019.8908066
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• A FPGA Implementation of Hard Systematic Error Correcting codes based Matching of Data Encoded Architecture with Low-Complexity, Low-Latency
  Second International Conference on Electronics, Communication and Aerospace Technology (ICECA) 2018 DOI: 10.1109/ICECA.2018.8474614
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