AY

Ashish Yadav

Shri Mata Vaishno Devi University

ORCID iD 0000-0002-4153-328X
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About

Graduate in Electronics and Communication engineering department at UGC affiliated Shri Mata Vaishno Devi University, Katra, Jammu & Kashmir.

Area of interest includes:
1. Process Variation Tolrent Circuit Design, Testing and Verification of VLSI Circuits Systems and Nano-Cmos technology, Low/Power/Process Aware VLSI Design.
2. Designing, implementation, analysis and operation of embedded systems, as well as developing experimental and prototype solutions.
3. Power Generation and Optimization,considering Renewable resource which are also cost effective.

Employment

Employment history is unavailable.

Education

  • Shri Mata Vaishno Devi University B-Tech
    2011 - 2015

Projects & Funding

Projects & funding information is unavailable.

Publications

Publications are unavailable.