LS
Laxmeesha Somappa
Also known as: Laxmeesha S
Indian Institute of Technology Bombay, EPFL - École Polytechnique Fédérale de Lausanne, Indian Institute of Technology Madras, Tata Elxsi (India)
Employment
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Indian Institute of Technology Bombay Assistant Professor2022 - Present
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EPFL - École Polytechnique Fédérale de Lausanne2021 - 2022
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EPFL - École Polytechnique Fédérale de Lausanne2021 - 2022
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Tata Elxsi (India) Memory modelling & Verification Engineer2011 - 2013
Education
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Indian Institute of Technology Bombay Ph.D2015 - 2021
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Indian Institute of Technology Madras M.Tech2013 - 2015
Projects & Funding
Projects & funding information is unavailable.
Publications (22)
- An Embedded Auto-Calibrated Offset Current Compensation Technique for PPG/fNIRS System Save
- Design of ESD Protection for Neuromodulation System-on-chip by Device Engineering in 65nm CMOS Technology Save
- ESD Protection With Sub-3Ω Dynamic Resistance for Neuromodulation System-on-Chip Save
- A highly sensitive mixed-signal auto-range adaptable interface for capacitive sensors Save
- Analog and Temporary On-chip Memory for ANN Training and Inference Save
- Hardware Optimization and Implementation of a 16-Channel Neural Tree Classifier for On-Chip Closed-Loop Neuromodulation Save
- Current-Excitation-Based ΔR-to-Frequency Converter for Resistive Sensors Save
- Design analysis and experimental validation of relaxation oscillator-based circuit for R–C sensors Save
- A Compact and Ultra-Low-Power Low-Pass Filter Based on Band-to-Band Tunneling Effect Save
- Enhanced regularization for on-chip training using analog and temporary memory weights Save