0000-0002-4338-6404 Employment
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Publications (32)
- FPGA fabric aware error detection and correction architecture design for BCD adder with minimal performance overhead Save
- Fast Bit-Sliced VLSI Architectures on FPGA for Montgomery Domain Modular Inversion Save
- Leveraging Dual Output LUTs with Pipelining for Efficient BCD to Binary Converter on FPGA Save
- Exploring Efficient BCD to Binary Conversion Architecture Alternatives on FPGA Save
- FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation Save
- FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion Save
- Design Automation for Tree-based Nearest Neighborhood-aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion Save
- Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support Save
- Primitive Instantiation for Speed-Area Efficient Architecture Design of Cellular Automata based Mageto Logic on FPGA with Built-In Testability Save
- Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-Up Tables Save