N Prasad

About

I am currently an institute doctoral student in the department of electronics and electrical communication engineering at the Indian Institute of Technology Kharagpur, Kharagpur. My broad area of research is in Reconfigurable Architecture Design.

Employment

Employment history is unavailable.

Education

• Indian Institute of Technology Kharagpur PhD
  2013 - Present
• National Institute of Technology Rourkela MTech
  2011 - 2013
• Gokaraju Rangaraju Institute of Engineering and Technology BTech
  2007 - 2011

Projects & Funding

Projects & funding information is unavailable.

Publications (16)

• A Parallel Stochastic Number Generator With Bit Permutation Networks
  IEEE Transactions on Circuits and Systems II: Express Briefs 2018 DOI: 10.1109/TCSII.2017.2708128
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• Design and evaluation of ZMesh topology for on-chip interconnection networks
  Journal of Parallel and Distributed Computing 2018 DOI: https://doi.org/10.1016/j.jpdc.2017.10.011
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• A New Logic Encryption Strategy Ensuring Key Interdependency
  2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID) 2017 DOI: 10.1109/VLSID.2017.29
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• Runtime mitigation of illegal packet request attacks in Networks-on-Chip
  2017 IEEE International Symposium on Circuits and Systems (ISCAS) 2017 DOI: 10.1109/ISCAS.2017.8050633
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• Approximate conditional carry adder for error tolerant applications
  2016 20th International Symposium on VLSI Design and Test (VDAT) 2016 DOI: 10.1109/ISVDAT.2016.8064867
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• Efficient VLSI Implementation of CORDIC-Based Direct Digital Synthesizer
  Intelligent Computing, Communication and Devices 2015
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• Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip
  Microprocessors and Microsystems 2015 DOI: https://doi.org/10.1016/j.micpro.2015.09.012
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• ZMesh: An Energy-Efficient Network-on-Chip Topology for Constant-Geometry Algorithms
  2015 IEEE International Symposium on Nanoelectronic and Information Systems 2015 DOI: 10.1109/iNIS.2015.16
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• Multiplier-less VLSI Architectures for Radix-$2^{2}$ Folded Pipelined Complex FFT Core
  Int. J. Circ. Theor. Appl. 2014 DOI: 10.1002/cta.2038
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• A spare link based reliable Network-on-Chip design
  18th International Symposium on VLSI Design and Test 2014 DOI: 10.1109/ISVDAT.2014.6881036
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