Sharad Sinha

Employment

• Indian Institute of Technology Goa Associate Professor
  2021 - Present
• Indian Institute of Technology (IIT) Assistant Professor
  2018 - 2021
• Nanyang Technological University Research Scientist
  2016 - 2018
• National University of Singapore Research Fellow
  2016 - 2016
• Hong Kong University of Science and Technology Visiting Scholar
  2014 - 2016
• Processor Systems (India) Pvt. Ltd. Design Engineer
  2007 - 2009

Education

• Nanyang Technological University PhD (Computer Engineering)
  2009 - 2013
• Cochin University of Science and Technology B.Tech (Electronics and Communication Engineering)
  2003 - 2007

Projects & Funding

Projects & funding information is unavailable.

Publications (27)

• PAAS: A system level simulator for heterogeneous computing architectures
  2017 27th International Conference on Field Programmable Logic and Applications (FPL) 2017 18 citations DOI: 10.23919/fpl.2017.8056775
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• My First Lecture and Other Lessons in Teaching
  IEEE Potentials 2017 0 citations DOI: 10.1109/mpot.2017.2662072
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• HeteroSim: A Heterogeneous CPU-FPGA Simulator
  IEEE Computer Architecture Letters 2017 15 citations DOI: 10.1109/lca.2016.2615617
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• Decision tree based hardware power monitoring for run time dynamic power management in FPGA
  2017 27th International Conference on Field Programmable Logic and Applications (FPL) 2017 11 citations DOI: 10.23919/fpl.2017.8056832
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• HeteroSim: A heterogeneous CPU-FPGA simulator
  2016 26th International Conference on Field Programmable Logic and Applications (FPL) 2016 3 citations DOI: 10.1109/fpl.2016.7577386
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• Low-Power FPGA Design Using Memoization-Based Approximate Computing
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2016 36 citations DOI: 10.1109/TVLSI.2016.2520979
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• Advanced\/Smart Manufacturing: From Nanoscale to Megascale
  IEEE Potentials 2016 2 citations DOI: 10.1109/mpot.2016.2540099
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• Area Efficient Hardware Architecture for Implicitly-Defined Complex Events Processing
  2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2016 0 citations DOI: 10.1109/isvlsi.2016.130
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• Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA
  Applied Reconfigurable Computing 2016 5 citations DOI: 10.1007/978-3-319-30481-6_13
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• Finding Happiness and Satisfaction During Your Ph.D. Program
  IEEE Potentials 2015 0 citations DOI: 10.1109/mpot.2015.2398471
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