Abhay Sharma

Employment

• Graphic Era University Associate Professor
  2022 - Present
• Graphic Era Hill University Assistant Professor
  2016 - 2017
• Anand Engineering College Assistant Professor
  2009 - 2013

Education

• University of Delhi Faculty of Technology Doctor of Philosophy
  2017 - 2022
• Motilal Nehru National Institute of Technology Master of technology
  2013 - 2015
• Visvesvaraya Technological University Bachelor of Engineering
  2003 - 2008

Projects & Funding

Projects & funding information is unavailable.

Publications (19)

• Optimal Design of Fractional-Order Digital Integrator using Lattice Wave Structure
  2022 8th International Conference on Signal Processing and Communication, ICSC 2022 2022 DOI: 10.1109/ICSC56524.2022.10009297
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• Triple Notch Filter using Non-Uniform Transmission Lines for UWB Applications
  2022 6th International Conference on Computing, Communication, Control and Automation, ICCUBEA 2022 2022 DOI: 10.1109/ICCUBEA54992.2022.10011019
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• FPGA Implementation of Lattice-Wave Half-Order Digital Integrator using Radix-2rDigit Recoding
  6th International Conference on Electronics, Communication and Aerospace Technology, ICECA 2022 - Proceedings 2022 DOI: 10.1109/ICECA55336.2022.10009223
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• Design and Implementation of Time Varying pole Radius IIR Notch filter with improved performance
  2020 2nd International Conference on Advances in Computing, Communication Control and Networking (ICACCCN) 2020 DOI: 10.1109/icacccn51052.2020.9362901
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• Design and FPGA implementation of lattice wave digital notch filter with minimal transient duration
  IET Signal Processing 2020 DOI: 10.1049/iet-spr.2020.0074
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• Notch/Peak filter Design and its FPGA Implementation through Wave Digital Structure
  2020 International Conference on Radar, Antenna, Microwave, Electronics, and Telecommunications (ICRAMET) 2020 DOI: 10.1109/ICRAMET51080.2020.9298644
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• Design and FPGA implementation of lattice wave fractional order digital differentiator
  Microelectronics Journal 2019 DOI: 10.1016/j.mejo.2019.04.013
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• Optimum Design and FPGA Implementation of Fractional Order Digital Integrator
  2019 6th International Conference on Signal Processing and Integrated Networks (SPIN) 2019 DOI: 10.1109/spin.2019.8711650
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• FPGA Implementation of High Speed Multiplier with Optimized Reduction Phase
  Advances in Intelligent Systems and Computing 2018 DOI: 10.1007/978-981-10-5903-2_21
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• Implementation of single precision conventional and fused floating point add-sub unit using Verilog
  Proceedings of the 2017 International Conference on Wireless Communications, Signal Processing and Networking, WiSPNET 2017 2018 DOI: 10.1109/WiSPNET.2017.8299741
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