Pallavi Paliwal

Employment

Employment history is unavailable.

Education

• Indian Institute of Technology
  2009 - Present

Projects & Funding

Projects & funding information is unavailable.

Publications (9)

• Fast Settling Phase-Locked Loops: A Comprehensive Survey of Applications and Techniques [Feature]
  IEEE Circuits and Systems Magazine 2024 DOI: 10.1109/MCAS.2024.3383809
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• Stability Analysis for Fast Settling Switched Digital Phase-Locked Loops (DPLLs)
  IEEE Control Systems Letters 2023 DOI: 10.1109/LCSYS.2023.3242830
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• A Fast Settling Fractional-$N$ DPLL With Loop-Order Switching
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2020 DOI: 10.1109/TVLSI.2019.2956100
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• A High-Resolution Digital Phase Interpolator Based CDR with a Half-Rate Hybrid Phase Detector
  2019 IEEE International Symposium on Circuits and Systems (ISCAS) 2019 DOI: 10.1109/iscas.2019.8702262
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• A low-jitter digital-to-time converter with look-ahead multi-phase DDS
  2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS) 2016 DOI: 10.1109/lascas.2016.7451049
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• A Fast Settling 4.7-5 GHz Fractional-N Digital Phase Locked Loop
  2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) 2016 DOI: 10.1109/vlsid.2016.48
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• High resolution digital-to-time converter for low jitter digital PLLs
  2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) 2014 DOI: 10.1109/icecs.2014.7049912
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• Tradeoffs between settling time and jitter in phase locked loops
  2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS) 2013 DOI: 10.1109/mwscas.2013.6674757
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• Circuit Optimization at 22nm Technology Node
  2012 25th International Conference on VLSI Design 2012 DOI: 10.1109/vlsid.2012.91
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