Maran Ponnambalam

Employment

• Amrita Vishwa Vidyapeetham University Assistant Professor (Sr.Gr)
  2021 - Present

Education

Education history is unavailable.

Projects & Funding

Projects & funding information is unavailable.

Publications (14)

• Correction to: Color image encryption based on novel kolam scrambling and modified 2D logistic cascade map (2D LCM)
  The Journal of Supercomputing 2023 DOI: 10.1007/s11227-023-05590-9
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• A color image encryption scheme using customized map
  The Imaging Science Journal 2023 DOI: 10.1080/13682199.2023.2182547
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• A two stage cascode LNA using modified derivative superposition technique in 0.13μm HBT with an IIP3 of 2 dBm and NF of 4.8 dB for IEEE 802.11ad standard
  Integration 2022 DOI: 10.1016/j.vlsi.2022.07.010
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• Variable gain wideband LNA in 130 nm SiGe HBT technology with stepped impedance micro-strip open circuited stubs for minimum transmission phase variation for WiGig phased array receivers
  Journal of Computational Electronics 2022 DOI: 10.1007/s10825-022-01916-7
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• Achieving high linearity and conversion gain in double balanced mixer with cascoded RF and LO stage
  Analog Integrated Circuits and Signal Processing 2021 DOI: 10.1007/s10470-020-01759-x
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• A Linear High Frequency g m Boosting Wideband LNA in 130 nm SiGe HBT with Minimum NF of 4.3 dB for WiGig Application
  Journal of Circuits, Systems and Computers 2021 DOI: 10.1142/S0218126622500013
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• Wideband inter-digitated hairpin resonating BPF with multiple CSRRs as DGS for harmonic suppression
  Analog Integrated Circuits and Signal Processing 2019 DOI: 10.1007/s10470-018-1301-7
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• Design and analysis of a narrowband hairpin shaped bandpass filter
  Proceedings of 2017 International Conference on Innovations in Information, Embedded and Communication Systems, ICIIECS 2017 2018 DOI: 10.1109/ICIIECS.2017.8276097
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• Comparison of tunability and phase noise associated with injection locked three staged single and differential ended VCOs in 90nm CMOS
  2017 4th International Conference on Signal Processing, Communication and Networking, ICSCN 2017 2017 DOI: 10.1109/ICSCN.2017.8085700
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• Improving HRR in 3P–8P harmonic rejection mixer using modified input transconductance stage in hard switching mixer
  Analog Integrated Circuits and Signal Processing 2017 DOI: 10.1007/s10470-017-0947-x
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