Abhishek Mukherjee

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Publications (7)

• A 3.7-mW 12.5-MHz 81-dB SNDR 4th-Order Continuous-Time DSM With Single-OTA and 2nd-Order Noise-Shaping SAR
  IEEE Open Journal of the Solid-State Circuits Society 2022 DOI: 10.1109/OJSSCS.2022.3212333
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• A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping
  IEEE Journal of Solid-State Circuits 2021 DOI: 10.1109/JSSC.2020.3038914
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• A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS
  IEEE Journal of Solid-State Circuits 2021 DOI: 10.1109/JSSC.2020.3012623
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• A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier
  IEEE Journal of Solid-State Circuits 2020 DOI: 10.1109/JSSC.2020.3020194
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• An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier
  IEEE Journal of Solid-State Circuits 2020 DOI: 10.1109/JSSC.2019.2960485
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• Design Tradeoffs for a CT-ΔΣ ADC With Hybrid Active–Passive Filter and FIR DAC in 40-nm CMOS
  IEEE Solid-State Circuits Letters 2020 DOI: 10.1109/LSSC.2020.3010985
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• A 1-GS/s 20 MHz-BW Capacitive-Input Continuous-Time $\Delta\Sigma$ ADC Using a Novel Parasitic Pole-Mitigated Fully Differential VCO
  IEEE Solid-State Circuits Letters 2019 DOI: 10.1109/LSSC.2019.2911874
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