MJ
Mohd Ziauddin Jahangir
Chaitanya Bharathi Institute of Technology, Osmania University University College of Engineering
Employment
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Chaitanya Bharathi Institute of Technology Assistant Professor2014 - Present
Education
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Osmania University University College of Engineering PhD2017 - Present
Projects & Funding
Projects & funding information is unavailable.
Publications (11)
- Design of novel hybrid - digitally controlled oscillator for ADPLL Save
- Study and Performance Comparison of Coupled Ring Oscillator Save
- Design and Implementation of FPGA based DDS-ADPLL for Resonant Frequency Tracking in Sensors Save
- The Design of DDS ADPLL using ARM Micro Controller Save
- Design of an All Digital Phase-Locked Loop Using Cordic Algorithm Save
- Design and simulation of an innovative CMOS ternary 3 to 1 multiplexer and the design of ternary half adder using ternary 3 to 1 multiplexer Save
- Design, implementation and performance comparison of different branch predictors on pipelined-CPU Save
- CMOS based design and simulation of ternary full adder and Ternary coded Decimal (TCD) adder circuit Save
- Design and simulation of programmable band-gap reference circuit Save
- Design of a new Ternary SRAM cell (ZV-SRAM) based on innovative level shift based Ternary Inverter (ZV-inverter) Save