Sandeep Mishra

About

A Smart Learner, like to function effectively and be able to deliver to the bottom-line. Always try to constantly upgrade my knowledge and skills and make a difference in whatever I do.

Employment

• Indian Institute of Information Technology Pune Assistant Professor
  2018 - Present
• National Institute of Technology Sikkim Assistant Professor
  2018 - 2018
• Gandhi Group of Institutions: Main Campus Lecturer
  2013 - 2014

Education

• National Institute of Technology Meghalaya Doctor of Philosophy
  2014 - 2018
• Biju Patnaik Univ. of Tech., School: GGI Main Campus M.Tech
  2011 - 2013
• Biju Patnaik Univ. of Tech., School: GGI Main Campus B.Tech
  2007 - 2011

Projects & Funding

Projects & funding information is unavailable.

Publications (28)

• Segmented Pre-Computation-Based CAM for Power-Efficient High-Speed Applications
  IEEE Transactions on Circuits and Systems I: Regular Papers 2026 DOI: 10.1109/TCSI.2026.3682601
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• SMS-CAM: Shared matchline scheme for content addressable memory
  Integration 2022 DOI: 10.1016/j.vlsi.2022.08.013
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• Match‐line control unit for power and delay reduction in hybrid CAM
  IET Circuits, Devices & Systems 2021 DOI: 10.1049/cds2.12024
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• A low power 10-bit ash analog-to-digital converter with divide and collate subranging conversion scheme
  Scientia Iranica 2021 DOI: 10.24200/sci.2019.5162.1129
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• Energy-Efficient Precharge-Free Ternary Content Addressable Memory (TCAM) for High Search Rate Applications
  IEEE Transactions on Circuits and Systems I: Regular Papers 2020 DOI: 10.1109/TCSI.2020.2978295
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• The analogy of matchline sensing techniques for content addressable memory (CAM)
  IET Computers & Digital Techniques 2020 DOI: 10.1049/iet-cdt.2019.0178
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• A novel low-power matchline evaluation technique for content addressable memory (CAM)
  Journal of Information Science and Engineering 2020 DOI: 10.6688/JISE.202009_36(5).0007
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• Low-power content addressable memory design using two-layer P-N match-line control and sensing
  Integration 2020 DOI: 10.1016/j.vlsi.2020.06.001
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• Pseudo-Static Master-Slave Match-Line Scheme for Sustainable-Performance and Energy-Efficient Content Addressable Memory
  2020 IEEE Region 10 Symposium, TENSYMP 2020 2020 DOI: 10.1109/TENSYMP50017.2020.9230943
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• Analysis of Analog Comparators Using a 6-Bit Flash ADC Architecture
  Lecture Notes on Data Engineering and Communications Technologies 2019 DOI: 10.1007/978-3-030-03146-6_3
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