AG

Anuj Grover

Indraprastha Institute of Information Technology, Delhi, STMicroelectronics (India), Indian Institute of Technology Delhi, University of California San Diego

ORCID iD 0000-0002-6057-4984
Follow

Employment

  • Indraprastha Institute of Information Technology, Delhi Associate Professor
    2019 - Present
  • STMicroelectronics (India) Principal Engineer
    2004 - 2019
  • STMicroelectronics (India) Design Engineer
    2000 - 2002

Education

  • Indian Institute of Technology Delhi PhD
    2010 - 2015
  • University of California San Diego MS
    2002 - 2003
  • Indian Institute of Technology Delhi B.Tech.
    1996 - 2000

Projects & Funding

Projects & funding information is unavailable.

Publications (87)

  • Tagged memory operated at lower vmin in error tolerant system
    2021
    +Save
  • Reduced March iC- Test for Detecting Ageing Induced Faults in Memory Address Decoders
    2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID) 2021 DOI: 10.1109/vlsid51830.2021.00038
    +Save
  • A 0.4 $μ$A Offset, 6ns Sensing-time Multi-level Sense Amplifier for Resistive Non-Volatile Memories in 65nm LSTP Technology
    2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID) 2021
    +Save
  • Reduced March iC-Test for Detecting Ageing Induced Faults in Memory Address Decoders
    2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID) 2021
    +Save
  • Memory computing, high-density array
    2021
    +Save
  • A 0.9 V 64Mb 6T SRAM cell with Read and Write assist schemes in 65nm LSTP technology
    2020 24th International Symposium on VLSI Design and Test (VDAT) 2020
    +Save
  • Diagnostic Circuit for Latent Fault Detection in SRAM Row Decoder
    2020 21st International Symposium on Quality Electronic Design (ISQED) 2020
    +Save
  • A 800MHz, O. 21pJ, 1.2 V to 6V Level Shifter Using Thin Gate Oxide Devices in 65nm LSTP
    2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) 2020
    +Save
  • AXI Based Three 8-bit Parallel Input to One Serial Output Converter with Priority Management System and Asynchronous Clocks at Input and Output
    2020 IEEE 17th India Council International Conference (INDICON) 2020
    +Save
  • Actively Compensated Read Assist Technique for 0.6 V Operation of 16 Mb High Density SRAM in 65nm LSTP
    2020 IEEE 17th India Council International Conference (INDICON) 2020
    +Save