Raghvendra Sahai Saxena
Also known as: R. S. Saxena, Raghvendra S. Saxena
DRDO Solid State Physics Laboratory, Indira Gandhi National Open University, Indian Institute of Technology Delhi, Indian Institute of Technology Bombay
About
Dr. Raghvendra Sahai Saxena was born in Etah district, Uttar Pradesh, India. After completing his B. E. degree in Electronics and Communication Engineering from G. B. Pant Engineering College, Uttarakhand in 1997, he joined Solid State Physics Laboratory (SSPL), Delhi in 1998. He received the M. Tech. degree in Microelectronics from Indian Institute of Technology (IIT), Bombay in 2003. He was awarded Prof. G. N. Revankar Prize by IIT Bombay for securing the highest marks in microelectronics (batch 2001-2003), Electrical Engineering Department, IIT Bombay. He received his Ph.D. degree in Design and Simulation of Trench Gate Power MOSFETs for RF and Switching Applications from IIT Delhi in 2012. He did post graduate diploma in applied statistics (PGDAST) from IGNOU in 2016, for which he received Gold Medal. He is American Society for Quality (ASQ) certified reliability engineer.
Since 1998, Dr. Saxena has been working at SSPL, where he is heading a research group working on the design, modeling and characterization of Infrared detectors and their readout circuits. He is a fellow of IETE and IEI. He is also a member of Semiconductor Society of India and International Association of Engineers.
Employment
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DRDO Solid State Physics Laboratory Scientist-F1998 - Present
Education
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Indira Gandhi National Open University Post Graduate Diploma in Applied Statistics (PGDAST)2015 - 2016
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Indian Institute of Technology Delhi PhD2006 - 2012
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Indian Institute of Technology Bombay M. Tech.2001 - 2003
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Govind Ballabh Pant Engineering College B.E.1993 - 1997
Projects & Funding
Projects & funding information is unavailable.
Publications (53)
- Co-optimization of nanotube tunnel FET performance for implementation in low-power complementary ternary inverter Save
- Investigation of Dielectric Properties of Quaternary Ceramic 0.47BNT-0.04BT-0.37PMN-0.18PT Save
- Pixel level suppression of dark current in gate modulation input ROIC for IRFPAs Save
- Analysing dielectric dispersion of 0.64PMN–0.36PT ceramics using electrical conductivity Save
- Fourier analysis of periodic signals using an Arduino-based low-cost portable setup Save
- An improved source follower per detector ROIC for HgCdTe infrared photodiodes Save
- A review of nanoindentation and related cathodoluminescence studies on semiconductor materials Save
- Dielectric dispersion near the morphotropic phase boundary of 0.64PMN-0.36PT ceramics Save
- CMOS Implementation of Time Delay Integration (TDI) for Imaging Applications: A Brief Review Save
- Cathodoluminescence Studies of Nanoindented CdZnTe Single Crystal Substrates for Analysis of Residual Stresses and Deformation Behaviour Save