Sujit Patel

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Publications (14)

• An efficient reconfigurable floating point multiplier design for signal processing applications
  Review of Computer Engineering Research 2026 DOI: 10.18488/76.v13i3.5085
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• Design of Frequency Sampling Rational Rate Polyphase FIR Converter
  IEEE Transactions on Circuits and Systems II: Express Briefs 2024 DOI: 10.1109/TCSII.2023.3309843
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• An area-delay efficient single-precision floating-point multiplier for VLSI systems
  Microprocessors and Microsystems 2023 DOI: 10.1016/j.micpro.2023.104798
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• Area-delay efficient Radix-4 8×8 Booth multiplier for DSP applications
  TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES 2021 DOI: 10.3906/elk-2007-179
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• A novel design of current differencing transconductance amplifier with high transconductance gain and enhanced bandwidth
  TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES 2021 DOI: 10.3906/elk-1909-125
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• Area-Delay and Energy Efficient Multi-operand Binary Tree Adder
  IET Circuits, Devices & Systems 2020 DOI: 10.1049/iet-cds.2019.0443
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• Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder
  Journal of Circuits, Systems and Computers 2020 DOI: 10.1142/s0218126620501868
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• A power and area efficient approximate carry skip adder for error resilient applications
  TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES 2020 DOI: 10.3906/elk-1907-72
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• An Efficient Accuracy Reconfigurable CLA Adder Designs Using Complementary Logic
  Journal of Electronic Testing 2020 DOI: 10.1007/s10836-019-05851-7
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• Area-Delay Efficient and Low-Power Carry Skip Adder for High Performance Computing Systems
  2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS) 2019 DOI: 10.1109/ises47678.2019.00074
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