Dr. Jailsingh Bhookya

About

Dr. Jailsingh Bhookya, Assistant Professor, Dept. of ECE, NIT Calicut, Kerala, India. He received a Ph.D. degree (2021) in Electronics and communications engineering from the National Institute of Technology Warangal, Telangana, India. He got a post-graduation degree M.Tech. (2011) in Digital Techniques & Instrumentation from Indian Institute of Technology (BHU) Varanasi, Uttar Pradesh, and graduation degree B.Tech. (2007) in Electronics and communications engineering from Jawaharlal Nehru Technological University Hyderabad, Telangana, India. His research interests include soft computing, Bio-Inspired optimization algorithm, Machine learning, optimal control techniques, Process control, Fractional-order modeling, and control. and IoT Applications.

Employment

• National Institute of Technology Calicut

Education

• Jawaharlal Nehru Technological University Hyderabad College of Engineering B.Tech
• Indian Institute of Technology (BHU) Varanasi M.Tech

Projects & Funding

Projects & funding information is unavailable.

Publications (10)

• Implementation of PID controller for liquid level system using mGWO and integration of IoT application
  Journal of Industrial Information Integration 2022 DOI: 10.1016/j.jii.2022.100368
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• PID controller design for decentralized Tito process using modified differential evolution algorithm
  Mechatronic Systems and Control 2021 DOI: 10.2316/J.2021.201-2947
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• Sine-cosine-algorithm-based fractional order PID controller tuning for multivariable systems
  International Journal of Bio-Inspired Computation 2021 DOI: 10.1504/IJBIC.2021.114088
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• Fractional Order PID Controller Design for Multivariable Systems using TLBO
  Chemical Product and Process Modeling 2020 DOI: 10.1515/cppm-2019-0061
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• Improved Jaya algorithm-based FOPID/PID for AVR system
  COMPEL - The International Journal for Computation and Mathematics in Electrical and Electronic Engineering 2020 DOI: 10.1108/COMPEL-08-2019-0319
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• Optimal FOPID/PID controller parameters tuning for the AVR system based on sine–cosine-algorithm
  Evolutionary Intelligence 2019 DOI: 10.1007/s12065-019-00290-x
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• Optimization and Effective analysis of Full Adder Circuit Design in 45nm Technology
  CVR Journal of Science and Technology 2015
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• Hazards and Glitch Power Reduction of CMOS Full Adder in 90nm Technology
  CVR Journal of Science and Technology 2014
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• Reduction of Static Power Dissipation in Adiabatic Combinational Circuits Using Power Gating MTCMOS
  International Journal of Advanced Trends in Computer Science and Engineering 2014
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• Sammon Mapping Based Neural Pre-Processing Scheme for On-Line Classification of Gases/Odors
  International Journal of Advanced Trends in Computer Science and Engineering 2014
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