LOMASH CHANDRA ACHARYA

Employment

• Indian Institute of Technology Roorkee

Education

Education history is unavailable.

Projects & Funding

Projects & funding information is unavailable.

Publications (17)

• A Methodology for Datapath Energy Prediction and Optimization in Near Threshold Voltage Regime
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2025 DOI: 10.1109/TVLSI.2024.3504856
  +Save
• Robust and Reliable Energy-Efficient Level Shifter
  IEEE Transactions on Circuits and Systems II: Express Briefs 2025 DOI: 10.1109/TCSII.2025.3547667
  +Save
• DAAS: Differential Aging-Aware STA for Precise Timing Closure With Reduced Design Margin
  IEEE Transactions on Device and Materials Reliability 2025 DOI: 10.1109/TDMR.2025.3603098
  +Save
• Switching Activity Factor-Based ECSM Characterization (SAFE): A Novel Technique for Aging-Aware Static Timing Analysis
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2024 DOI: 10.1109/TCAD.2024.3396432
  +Save
• Unveiling the mechanism behind the negative capacitance effect in Hf0.5Zr0.5O2-Based ferroelectric gate stacks and introducing a Circuit-Compatible hybrid compact model for Leakage-Aware NCFETs
  Solid-State Electronics 2024 DOI: 10.1016/j.sse.2024.108932
  +Save
• Influences of Source/Drain Extension Region on Thermal Behavior of Stacked Nanosheet FET
  IEEE Transactions on Electron Devices 2024 DOI: 10.1109/TED.2024.3351596
  +Save
• Prediction of variation aware F in ring oscillators (ROs) to mitigate the impact of aging on RO-PUF
  Solid-State Electronics 2023 DOI: 10.1016/j.sse.2023.108790
  +Save
• Generalized Edge Propagation and Multi-Band Frequency Switching Mechanism for MSSROs
  IEEE Transactions on Circuits and Systems II: Express Briefs 2023 DOI: 10.1109/TCSII.2023.3267384
  +Save
• Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure
  2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2023 DOI: 10.1109/smacd58065.2023.10192158
  +Save
• Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2023 DOI: 10.1109/TCAD.2022.3231173
  +Save