MAYANK KUMAR SINGH

Employment

• Indian Institute of Technology Ropar

Education

• Indian Institute of Technology Ropar Ph.D.
  2019 - Present
• Pondicherry University M.Tech.
  2016 - 2018
• Invertis University B.Tech.
  2011 - 2015

Projects & Funding

Projects & funding information is unavailable.

Publications (12)

• A 0.024 $mm^{2}$, 294 $\mu$W, Resistor Weighted Curvature Corrected Bandgap Reference
  Integrated Circuits and Systems 2026 DOI: 10.23919/ICS.2026.3667472
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• A 15.4 ppm/°C Improved Current Mode Bandgap with 0.9 V Supply in 28 nm CMOS
  International Conference on Integrated Circuits, Communication, and Computing Systems (ICIC3S) 2024 DOI: 10.1109/ICIC3S61846.2024.10603389
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• A Noise and Mismatch Improved Charge Pump for PLL in 28nm CMOS Technology
  International Conference on Integrated Circuits, Communication, and Computing Systems (ICIC3S) 2024 DOI: 10.1109/ICIC3S61846.2024.10602954
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• An RC-based Dual Injection Locked Delay Cell for High-Frequency Ring VCOs
  Proceedings of the Irish Signals and Systems Conference (ISSC) 2024 DOI: 10.1109/ISSC61953.2024.10603085
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• A PRBS Generator Using Merged XOR-D Flip-Flop as Building Blocks
  Circuits, Systems, and Signal Processing 2023 DOI: 10.1007/s00034-023-02425-z
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• A Low Power Differential Delay Cell without Cross-Coupled Latch for Ring VCO
  2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) 2023 DOI: 10.1109/prime58259.2023.10161983
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• Frequency Range Enhancement in Differential Ring VCO while Maintaining Phase Noise Performance
  IEEE Techrxiv 2023 DOI: 10.36227/techrxiv.22360546.v1
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• A Differential Delay Cell for Ring Oscillators
  IEEE Techrxiv 2023 DOI: 10.36227/techrxiv.22003907.v1
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• An active inductor employed CML latch for high speed integrated circuits
  Analog Integrated Circuits and Signal Processing 2022 DOI: 10.1007/s10470-022-02070-7
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• A low power 8 × 27-1 PRBS generator using Exclusive-OR gate merged D flip-flops
  Midwest Symposium on Circuits and Systems 2021 DOI: 10.1109/MWSCAS47672.2021.9531827
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