Gaurav Purohit

About

I am Gaurav Purohit (a.k.a GP). My area of expertise in Wireless communication domain especially in physical layer baseband architecture design. I completed my doctorate in Energy-efficient digital baseband design for software-defined radio. Currently, my area of interest is LDPC and polar coding (5G and B5G, intermediate), AI data modelling with air quality data (AI intermediate) , bit manipulated low power architecure design (FPGA expertise) and IoT applications (beginner level)

Employment

• Central Electronics Engineering Research Institute CSIR Scientist/ Programmer/ designer
  2016 - Present
• Birla Institute of Technology and Science Senior research fellow
  2011 - 2016

Education

Education history is unavailable.

Projects & Funding

Projects & funding information is unavailable.

Publications (10)

• Flexible Piezoresistive Strain Sensors Using Ternary Conductive Hybrid Nanocomposites Integrated Into Wearable Smart Gloves for Human–Machine Interface
  IEEE Sensors Journal 2026 DOI: 10.1109/JSEN.2025.3645819
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• Design and Development of Real-Time IoT-Cloud Integrated Vehicle Number Plate Recognition System
  2026 DOI: 10.1007/978-981-95-3495-1_31
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• FPGA-Based Implementation of Single-Cycle High-Throughput LDPC Encoder for 5G New Radio
  IEEE Embedded Systems Letters 2025 DOI: 10.1109/LES.2025.3546543
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• XOR-Free Approach for Implementation of Polar Encoder
  IEEE Embedded Systems Letters 2025 DOI: 10.1109/LES.2024.3495657
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• An Edge Computing-Assisted Internet of Things-Based Secure Smart Home
  2022 DOI: 10.1007/978-981-16-7182-1_14
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• A New XOR-FREE Approach to Implement Walsh Sequences
  Wireless Personal Communications 2019 DOI: 10.1007/s11277-019-06549-x
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• Transition sequence based Walsh Encoder: A novel power efficient architecture
  Microprocessors and Microsystems 2018 DOI: 10.1016/j.micpro.2018.08.003
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• A New XOR-Free Approach for Implementation of Convolutional Encoder
  IEEE Embedded Systems Letters 2016 DOI: 10.1109/les.2015.2499207
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• XOR-FREE Implementation of Convolutional Encoder for Reconfigurable Hardware
  International Journal of Reconfigurable Computing 2016 DOI: 10.1155/2016/9128683
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• FPGA based implementation & power analysis of parameterized Walsh sequences
  Proceedings of the 2014 IEEE Students' Technology Symposium 2014 DOI: 10.1109/techsym.2014.6808063
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