Employment
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National Institute of Technology Warangal
Education
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Publications (8)
- Design and temperature assessment of analog/RF and linearity parameters on dual material gate junctionless FinFET at 7 nm technology node for nano scale applications Save
- Efficient computation and design of high speed double precision Vedic multiplier architecture Save
- A Novel Reversible Gate Design for Comprehensive Logic and Arithmetic Operations Save
- Study of DMG JLFinFET: Analog/RF Perspective at 7nm Technology Node Save
- Dimensional Effect on Analog/RF Performance of Dual Material Gate Junctionless FinFET at 7 nm Technology Node Save
- Design and Optimization of Dual Material Gate Junctionless FinFET Using Dimensional Effect, Gate Oxide and Workfunction Engineering at 7 nm Technology Node Save
- Performance analysis of FinFET using gate stack and workfunction engineering in 14nm technology Save
- Statistical (M-C) and Static noise margin analysis of the SRAM cells Save