ASHRAF MANIYAR

About

Ashraf Maniyar is an Institute Postdoctoral Fellow in the Department of Electrical Engineering at the Indian Institute of Technology Kanpur, India. He received his Ph.D. in Microelectronics from the Indian Institute of Technology Patna, where his research focused on the impact of fabrication-induced sidewall geometry on the leakage current, thermal noise, and analog/RF performance of Gate-All-Around (GAA) nanowire MOSFETs. His research interests include semiconductor device characterization, TCAD simulation, compact modeling, parameter extraction, and advanced CMOS device technologies. He has authored several research articles in leading journals, including IEEE Transactions on Electron Devices, Silicon, Microelectronics Journal, and RSC Advances. His current research focuses on compact model parameter extraction and validation using industry-standard models such as BSIM4 and BSIM-Bulk with Keysight IC-CAP for circuit design and PDK development.

Employment

• IIT Kanpur IPDF
  2026 - 2027

Education

• Indian Institute of Technology Patna PHD
  2020 - 2025
• National Institute of Technology Kurukshetra M.TECH
  2018 - 2020
• National Institute of Technology Nagaland B,TECH
  2012 - 2016

Projects & Funding

Projects & funding information is unavailable.

Publications (11)

• Investigation of the RF Performance of n-JL (Junctionless) CombFETwith Ambient Temperature Variations
  2026 DOI: 10.21203/rs.3.rs-9433679/v1
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• Geometry-Driven Thermal Noise Trends in GAA Nanowire Devices
  SILICON 2026 DOI: 10.1007/S12633-026-03662-Y
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• Investigation of dual-metal/dielectric with III-V heterojunction extended-source gate-all-around vertical TFET for enhanced electrical performance
  MICRO AND NANOSTRUCTURES 2026 DOI: 10.1016/J.MICRNA.2026.208752
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• DC Performance Benchmarking of Core-Insulator Embedded Junctionless NSFETS for Low-Power Logic Applications
  2025 13th International Conference on Intelligent Embedded, MicroElectronics, Communication and Optical Networks (IEMECON) 2025 DOI: 10.1109/iemecon69302.2025.11365887
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• A Quasi-3D Model of Gate-Induced Drain Leakage Current of a Trapezoidal GAA MOSFET
  JOURNAL OF ELECTRONIC MATERIALS 2025 DOI: 10.1007/S11664-025-12403-7
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• Microelectronic Devices and Technologies (MicDAT 2025)
  Unpublished 2025 DOI: 10.13140/RG.2.2.25110.61767
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• Si/SiGe superlattice-based double gate feedback field-effect transistor and its application in 1T-DRAM
  MICROELECTRONICS JOURNAL 2025 DOI: 10.1016/J.MEJO.2025.106822
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• Impact of Process-Induced Inclined Side-Walls on Gate Leakage Current of Nanowire GAA MOSFETs
  IEEE TRANSACTIONS ON ELECTRON DEVICES 2024 DOI: 10.1109/TED.2024.3357434
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• Impact of Process-Induced Inclined Sidewalls On Small Signal Parameters of Silicon Nanowire GAA MOSFET
  TENCON 2023 - 2023 IEEE Region 10 Conference (TENCON) 2023 DOI: 10.1109/tencon58879.2023.10322347
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• Impact of Process-Induced Inclined Sidewalls on Gate-Induced Drain Leakage (GIDL) Current of Nanowire GAA MOSFETs
  IEEE TRANSACTIONS ON ELECTRON DEVICES 2022 DOI: 10.1109/TED.2022.3194109
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