Devarshi Mrinal Das

About

I am an Assistant Professor in the Department of Electrical Engineering at the Indian Institute of Technology (IIT) Ropar, India. I have received an M.Tech degree from IIT Delhi in 2010 and a PhD degree from IIT Bombay in 2017. My PhD thesis focused on the design and development of low-power and low-noise analog signal conditioning integrated circuits. My PhD supervisor was Prof. Maryam Shojaei Baghini. From 2010 to 2012, I worked as a Design Engineer in the Advanced Technology Organisation (ATO) lab of General Electric (GE). From 2017 to 2018, I worked as a Lead Research Engineer in the Corporate Technology (CT) group of Siemens. My research interest is multidisciplinary, which includes CMOS integrated circuit design, neuromorphic electronics, electronic system design for high precision instrumentation, bio-medical instrumentation, sensors and transducers. I have published more than 20 journal/conference papers as author/co-author and have filed for several patents. I am a senior member of IEEE and also an active reviewer for many reputed journals, including IEEE Trans. on Circuits and Systems - 1, IEEE Trans. on Neural Networks and Learning Systems, IEEE Trans. on Biomedical Circuits and Systems, IEEE Trans. on Instrumentation and Measurements, IEEE Sensors Journal, Elsevier Microelectronics Journal, IET Electronics Letters and others. I was awarded as one of the "Outstanding Reviewers of 2019" by the IEEE Transactions on Instrumentation and Measurement Society.

Employment

• Indian Institute of Technology Ropar Assistant Professor
  2018 - Present
• Siemens (Germany) Lead Research Engineer
  2017 - 2018
• General Electric (India) Design Engineer
  2010 - 2012

Education

• Dharmsinh Desai University
  2002 - 2006

Projects & Funding

Projects & funding information is unavailable.

Publications (74)

• A 0.024 $mm^{2}$, 294 $\mu$W, Resistor Weighted Curvature Corrected Bandgap Reference
  Integrated Circuits and Systems 2026 DOI: 10.23919/ICS.2026.3667472
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• A Mode-Selective Rail-to-Rail Dynamic Comparator Featuring Cross-Coupled Pre-Amplifierswith <153 ps Delay and <77 fJ⋅ns EDP
  2026 DOI: 10.2139/ssrn.7139680
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• Mitigating EMI Susceptibility in Three OpAmp INA With a High CMRR EMI Immune OTA
  IEEE Transactions on Electromagnetic Compatibility 2026 DOI: 10.1109/TEMC.2026.3677893
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• Analysis and design of an optimum CMRR neural amplifier and a figure of merit for noise and area optimization
  Integration 2026 DOI: 10.1016/j.vlsi.2026.102805
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• Enhancing Resistive Switching Characteristics of MoS₂-Based Memristor Through O₂ Plasma Irradiation-Induced Defects
  IEEE Journal of the Electron Devices Society 2025 DOI: 10.1109/JEDS.2024.3480356
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• Intelligent Analog and Mixed-Signal IC (I-AMS-IC) Design: A Conceptual Framework, and Case Study on AI Integration
  Is3c 2025 International Symposium on Computer Consumer and Control 2025 DOI: 10.1109/IS3C65361.2025.11131067
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• A 2.9 mW Inverter-based Quadrature Phase Clock Generator with ± 0.29° Phase Error
  2025 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2025 DOI: 10.1109/ISCAS56072.2025.11043332
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• SpiMAM: CMOS Implementation of Bio-Inspired Spiking Multidirectional Associative Memory Featuring In-Situ Learning
  IEEE Transactions on Circuits and Systems I: Regular Papers 2025 DOI: 10.1109/TCSI.2024.3427387
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• A low-power common-mode insensitive rail-to-rail dynamic comparator for ADCs
  Integration 2025 DOI: 10.1016/j.vlsi.2024.102288
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• Impact of EMI on the Reliability of Crossbar Architecture-Based Inference in CMOS Technology
  IEEE Transactions on Components, Packaging and Manufacturing Technology 2025 DOI: 10.1109/TCPMT.2025.3559486
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