Anuj Vaishnav

About

He works on FPGA virtualisation for Cloud computing, as a part of Advanced Processor Technology group at The University of Manchester and is supervised by Dr Dirk Koch and Dr James Garside. His research focuses on the transparent provision of flexible resource sharing among accelerators for maximising resource utilisation to improve performance and energy efficiency.

Employment

Employment history is unavailable.

Education

• The University of Manchester PhD in Computer Science
  2017 - Present
• The University of Manchester BEng (Hons) Computer Systems Engineering
  2014 - 2017

Projects & Funding

Projects & funding information is unavailable.

Publications (9)

• FOS: A Modular FPGA Operating System for Dynamic Workloads
  ACM Transactions on Reconfigurable Technology and Systems 2020 DOI: 10.1145/3405794
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• Heterogeneous Resource-Elastic Scheduling for CPU+FPGA Architectures
  Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies - HEART 2019 2019 DOI: 10.1145/3337801.3337819
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• ZUCL 2.0: Virtualised Memory and Communication for ZYNQ UltraScale+ FPGAs
  FSP Workshop 2019; Sixth International Workshop on FPGAs for Software Programmers 2019
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• Live Migration for OpenCL FPGA Accelerators
  2018 International Conference on Field-Programmable Technology (FPT) 2018 DOI: 10.1109/fpt.2018.00017
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• IPRDF: An Isolated Partial Reconfiguration Design Flow for Xilinx FPGAs
  IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2018) 2018 DOI: 10.1109/MCSoC2018.2018.00018
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• ZUCL: A ZYNQ UltraScale+ Framework for OpenCL HLS Applications
  Fifth International Workshop on FPGAs for Software Programmers (FSP 2018) 2018
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• A Survey on FPGA Virtualization
  2018 28th International Conference on Field Programmable Logic and Applications (FPL) 2018 DOI: 10.1109/FPL.2018.00031
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• Resource Elastic Virtualization for FPGAs Using OpenCL
  2018 28th International Conference on Field Programmable Logic and Applications (FPL) 2018 DOI: 10.1109/FPL.2018.00028
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• A security library for FPGA interlays
  2017 27th International Conference on Field Programmable Logic and Applications (FPL) 2017 DOI: 10.23919/fpl.2017.8056817
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