Nagendra Krishnapura

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Publications (48)

• Low 1/f³ Phase Noise Quadrature LC VCOs
  IEEE Transactions on Circuits and Systems I: Regular Papers 2018 DOI: 10.1109/TCSI.2017.2782247
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• A 2-GHz Bandwidth, 0.25-1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13 \mu m CMOS
  IEEE Journal of Solid-State Circuits 2017 DOI: 10.1109/JSSC.2017.2693229
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• A 500Mb/s 200pJ/b die-to-die bidirectional link with 24kV surge isolation and 50kV/µs CMR using resonant inductive coupling in 0.18µm CMOS
  Digest of Technical Papers - IEEE International Solid-State Circuits Conference 2017 DOI: 10.1109/ISSCC.2017.7870447
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• A Low Power Multi-channel Input Delta-Sigma ADC without Reset
  Proceedings - 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems, VLSID 2017 2017 DOI: 10.1109/VLSID.2017.85
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• Optimum scaling of stages in a frequency divider chain for best jitter FoM
  Proceedings - IEEE International Symposium on Circuits and Systems 2017 DOI: 10.1109/ISCAS.2017.8051001
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• Session 12-Analog techniques i
  Proceedings of the Custom Integrated Circuits Conference 2017 DOI: 10.1109/CICC.2017.7993608
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• A 12.5 mW, 11.1 nV/√Hz, -115 dB THD, < 1 μs Settling, 18 bit SAR ADC Driver in 0.6 μm CMOS
  IEEE Transactions on Circuits and Systems II: Express Briefs 2016 DOI: 10.1109/TCSII.2015.2504024
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• A tail-resonance calibration technique for wide tuning range LC VCOs
  Proceedings - IEEE International Symposium on Circuits and Systems 2016 DOI: 10.1109/ISCAS.2016.7538986
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• Accurate Constant Transconductance Generation without Off-Chip Components
  Proceedings of the IEEE International Conference on VLSI Design 2015 DOI: 10.1109/VLSID.2015.48
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• Gain enhanced high frequency OTA with on-chip tuned negative conductance load
  Proceedings - IEEE International Symposium on Circuits and Systems 2015 DOI: 10.1109/ISCAS.2015.7169089
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