Rijoy Mukherjee

About

I am currently a Staff R&D Engineer at Synopsys, part of the VC Formal R&D team, working specifically on the application of generative AI for next-gen formal verification of hardware. Prior to joining Synopsys, I completed my Ph.D. from the Dept of CSE at IIT Kharagpur, advised by Prof. Rajat Subhra Chakraborty. I was awarded the Prime Minister Research Fellowship (PMRF) during my Ph.D. tenure. My research focuses on exploring generative AI methodologies for advancing electronic design automation (EDA) workflows. I am particularly interested in leveraging large language models (LLMs) to aid and automate various computer-aided design tasks, including hardware design and verification.

Employment

• Synopsys Staff Engineer
  2025 - Present
• Polaris Networks Software Engineer
  2016 - 2019

Education

• IIT Kharagpur PhD
  2019 - 2025
• NIT Durgapur B TECH
  2012 - 2016

Projects & Funding

Projects & funding information is unavailable.

Publications (22)

• Detecting Hardware Trojans in High-Level Synthesis-Generated RTL using Large Language Models
  ACM Transactions on Design Automation of Electronic Systems 2026 DOI: 10.1145/3795509
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• Evaluating Large Language Models for Automatic Register Transfer Logic Generation for Combinational Circuits via High-Level Synthesis
  Foundations and Trends in Electronic Design Automation 2025 DOI: 10.1561/1000000063-3
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• FPGA Security
  Encyclopedia of Cryptography Security and Privacy Third Edition 2025 DOI: 10.1007/978-3-030-71522-9_1644
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• Evaluating Large Language Models for Automatic Register Transfer Logic Generation via High-Level Synthesis
  Arxiv 2024 DOI: 10.48550/arXiv.2408.02793
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• HLS-IRT: Hardware Trojan Insertion through Modification of Intermediate Representation During High-Level Synthesis
  ACM Transactions on Design Automation of Electronic Systems 2024 DOI: 10.1145/3663477
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• Security Vulnerabilities in AI Hardware: Threats and Countermeasures
  Proceedings of the Asian Test Symposium 2024 DOI: 10.1109/ATS64447.2024.10915219
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• Attacks on Recent DNN IP Protection Techniques and Their Mitigation
  IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems 2023 DOI: 10.1109/TCAD.2023.3272271
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• A comprehensive survey of physical and logic testing techniques for Hardware Trojan detection and prevention
  Journal of Cryptographic Engineering 2022 DOI: 10.1007/s13389-022-00295-w
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• Novel Hardware Trojan Attack on Activation Parameters of FPGA-Based DNN Accelerators
  IEEE Embedded Systems Letters 2022 DOI: 10.1109/LES.2022.3159541
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• APUF-BNN: An Automated Framework for Efficient Combinational Logic Based Implementation of Arbiter PUF through Binarized Neural Network
  Proceedings of the ACM Great Lakes Symposium on VLSI Glsvlsi 2021 DOI: 10.1145/3453688.3461484
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