Subir Kumar Maity

About

Dr. Subir Kr. Maity has more than thirteen years of academic experience. He completed his Ph.D. from the Institute of Radio Physics and Electronics, University of Calcutta, Kolkata in the area of nano-scale MOSFET with III-V compound semiconductor as channel material. His search interests are compact modeling of sub-micron MOSFET, MOS transistor with high mobility channel, quantum well MOSFET, Negative Capacitance FETs, Artificial Neural network based compact model development, etc.

Employment

• Kalinga Institute of Industrial Technology Deemed to be University Associate Professor
  2012 - Present

Education

• University of Calcutta Ph.D
  2017 - 2023
• Jadavpur University Faculty of Engineering and Technology M.Tech
  2008 - 2011

Projects & Funding

Projects & funding information is unavailable.

Publications (51)

• The role of asymmetry in elevating nanosheet FET: RF and circuit metrics
  Analog Integrated Circuits and Signal Processing 2026 DOI: 10.1007/s10470-026-02614-1
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• Spacer engineering approach for performance enhancement of tree-based nanosheet FETs - a numerical simulation-based study
  Engineering Research Express 2026 DOI: 10.1088/2631-8695/ae444e
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• Bridging TCAD and AI: A Machine Learning Approach for BioTFET Behavior Prediction
  IEEE Transactions on Nanotechnology 2026 DOI: 10.1109/TNANO.2026.3720723
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• Investigating Pocket-Engineered Tree-Based NSFETs With Asymmetric Spacers
  IEEE Access 2026 DOI: 10.1109/ACCESS.2026.3726671
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• Performance Reliability of Ge Nanosheet FETs for Gaussian Distribution Channel Incorporating Interface Trap for RF and Analog Application
  IEEE Access 2026 DOI: 10.1109/ACCESS.2026.3705225
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• Comparative analysis of nanowire and nanosheet FETs: assessing analog, RF and circuit performance benchmarks
  Engineering Research Express 2026 DOI: 10.1088/2631-8695/ae8742
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• Low Power Priority Encoder with Forced-Leakage Control NMOS Transistor Technique
  2025 5th IEEE International Conference on Applied Electromagnetics, Signal Processing, & Communication (AESPC) 2025 DOI: 10.1109/AESPC67542.2025.11326697
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• RF and Circuit Performance Study of InGaAs Core-shell FinFET
  Proceedings of 6th International Conference on 2025 Devices for Integrated Circuit, DevIC 2025 2025 DOI: 10.1109/DevIC63749.2025.11012228
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• Optimizing Double Channel FinFETs: The Role of Source/Drain Asymmetry
  2025 5th IEEE International Conference on Applied Electromagnetics, Signal Processing, & Communication (AESPC) 2025 DOI: 10.1109/AESPC67542.2025.11326901
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• Impact of Gate-Source/Drain Underlap on Device Performance of Germanium Nanosheet FETs
  2025 2nd International Conference on Circuits, Power and Intelligent Systems (CCPIS) 2025 DOI: 10.1109/CCPIS65231.2025.11233858
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