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VLSI design of fixed width 2's compliment multiplier
Proceedings of 2017 International Conference on Innovations in Information, Embedded and Communication Systems, ICIIECS 2017 2018 DOI: 10.1109/ICIIECS.2017.8276148
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Probablity and simulation based design of fixed width multiplier
Proceedings of the International Conference on Electronics, Communication and Aerospace Technology, ICECA 2017 2017 DOI: 10.1109/ICECA.2017.8203697
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An efficient design of redundant binary modified partial product generator
Conference on Advances in Signal Processing, CASP 2016 2016 DOI: 10.1109/CASP.2016.7746212
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High performance redundant binary multiplier
International Conference on Communication and Signal Processing, ICCSP 2016 2016 DOI: 10.1109/ICCSP.2016.7754358
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VLSI design of 64bit × 64bit high performance multiplier with redundant binary encoding
Proceedings - 2016 International Conference on Advances in Computing, Communication and Automation (Fall), ICACCA 2016 2016 DOI: 10.1109/ICACCAF.2016.7748971
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Design of error-compensated fixed-width multiplier
2015 International Conference on Communication and Signal Processing, ICCSP 2015 2015 DOI: 10.1109/ICCSP.2015.7322804
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Design of polyphase FIR filter using bypass feed direct multiplier
2015 International Conference on Communication and Signal Processing, ICCSP 2015 2015 DOI: 10.1109/ICCSP.2015.7322796
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Design of FPGA based instruction fetch & decode module of 32-bit RISC (MIPS) processor
Proceedings - 2011 International Conference on Communication Systems and Network Technologies, CSNT 2011 2011 DOI: 10.1109/CSNT.2011.91
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VLSI design of analog multiplier based on NMOS technology
International Conference and Workshop on Emerging Trends in Technology 2011, ICWET 2011 - Conference Proceedings 2011 DOI: 10.1145/1980022.1980285
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